Semiconductor package with switch node integrated heat spreader

Patent metadata

Field	Value
Publication number	US-9502338-B2
Application number	US-201514795527-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Nov 8, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a patterned conductive carrier;
a control FET having a control drain attached to a first segment of said patterned conductive carrier;
a sync FET having a sync source attached to a second segment of said patterned conductive carrier;
a heat spreading conductive plate situated over a control source of said control FET and over a sync drain of said sync FET so as to couple said control source and said sync drain to a switch node segment of said patterned conductive carrier.

2. The semiconductor package of claim 1 , wherein said first and second segments of said patterned conductive carrier are respectively first and second partially etched segments.

3. The semiconductor package of claim 1 , wherein said control FET and said sync FET form a power switching stage of a voltage converter.

4. The semiconductor package of claim 1 , wherein said heat spreading conductive plate comprises a substantially flat metal plate.

5. The semiconductor package of claim 1 , wherein said control source, said sync drain, and a top surface of said switch node segment are substantially coplanar.

6. The semiconductor package of claim 1 , wherein said patterned conductive carrier comprises at least a portion of a lead frame.

7. The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise silicon FETs.

8. The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise III-Nitride FETs.

9. The semiconductor package of claim 1 , wherein a control gate of said control FET is coupled to another segment of said patterned conductive carrier.

10. The semiconductor package of claim 9 , wherein said another segment of said patterned conductive carrier is another partially etched segment.

11. A semiconductor package comprising:
a patterned conductive carrier;
a control FET and a sync FET;
a heat spreading conductive plate situated over a control source of said control FET and over a sync drain of said sync FET so as to couple said control source and said sync drain to a switch node segment of said patterned conductive carrier.

12. The semiconductor package of claim 11 , wherein said control FET and said sync FET form a power switching stage of a voltage converter.

13. The semiconductor package of claim 11 , wherein said heat spreading conductive plate comprises a substantially flat metal plate.

14. The semiconductor package of claim 11 , wherein said control source, said sync drain, and a top surface of said switch node segment are substantially coplanar.

15. The semiconductor package of claim 11 , wherein said patterned conductive carrier comprises at least a portion of a lead frame.

16. The semiconductor package of claim 11 , wherein said control FET and said sync FET comprise silicon FETs.

17. The semiconductor package of claim 11 , wherein said control FET and said sync FET comprise III-Nitride FETs.

18. A method for fabricating a semiconductor package, said method comprising:
providing a patterned conductive carrier;
attaching a control drain of a control FET to a first segment of said patterned conductive carrier;
attaching a sync source of a sync FET to a second segment of said patterned conductive carrier;
situating a heat spreading conductive plate over a control source of said control FET and over a sync drain of said sync FET, said heat spreading conductive plate coupling said control source and said sync drain to a switch node segment of said patterned conductive carrier.

19. The method of claim 18 , wherein said first and second segments of said patterned conductive carrier are respectively first and second partially etched segments.

20. The method of claim 18 , wherein said patterned conductive carrier comprises at least a portion of a lead frame.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San
• Clavette Dan

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title