Coreless substrate with passive device pads

Patent metadata

Field	Value
Publication number	US-9502336-B2
Application number	US-201313801822-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

First claim

What is claimed is:

1. A package assembly comprising:
a coreless substrate comprising a first side, a second side opposite to the first side, and a plurality of build-up layers between the first side and the second side;
two or more passive device pads disposed on the first side of the coreless substrate, wherein each of the two or more passive device pads has a first surface and a second surface, and, for each of the two or more passive device pads, the second surface is disposed between the first surface and the coreless substrate;
an electrical routing feature disposed on the second side of the coreless substrate;
a first solder resist layer disposed on the first side of the coreless substrate, wherein the first solder resist layer has a first surface and a second surface, the second surface of the first solder resist layer is disposed between the first surface of the first solder resist layer and the coreless substrate, the two or more passive device pads are disposed within corresponding openings in the first solder resist layer, and the first surfaces of the two or more passive device pads are recessed from the first surface of the first solder resist layer; and
an electrical path defined in the plurality of build-up layers to route an electrical power between the two or more passive device pads and the electrical routing feature;
wherein the electrical path includes a conductive element disposed on or within the build-up layers and adjacent to the first solder resist layer, the two or more passive device pads being conductively coupled to the conductive element.

2. The package assembly of claim 1 , further comprising a second solder resist layer disposed on the second side of the coreless substrate, the electrical routing feature disposed within a corresponding opening in the second solder resist layer.

3. The package assembly of claim 1 , further comprising a dielectric layer disposed on the first side of the coreless substrate and a solder resist layer disposed on the second side of the coreless substrate, the two or more passive device pads disposed within corresponding openings in the dielectric layer, and the electrical routing feature disposed within a corresponding opening in the solder resist layer.

4. The package assembly of claim 1 , wherein the two or more passive device pads are capacitor pads, the package assembly further including a decoupling capacitor coupled with one of the two or more capacitor pads.

5. The package assembly of claim 4 , wherein the electrical routing feature disposed on the second side of the coreless substrate is a first electrical routing feature and the electrical path is a first electrical path, the package assembly further comprising:
a second electrical routing feature disposed on the first side of the coreless substrate;
a third electrical routing feature disposed on the second side of the coreless substrate; and
a second electrical path defined in the plurality of build-up layers to route electrical signals between the second electrical routing feature on the first side of the coreless substrate and the third electrical routing feature on the second side of the coreless substrate.

6. The package assembly of claim 5 , wherein the second electrical routing feature is a pad to route electrical signals of one or more dies.

7. The package assembly of claim 1 , wherein the conductive element is a trace.

8. The package assembly of claim 1 , wherein the conductive element is formed of a metal.

9. The package assembly of claim 1 , wherein the conductive element is formed of copper.

10. The package assembly of claim 1 , wherein the conductive element is formed by an electrolytic plating process.

11. The package assembly of claim 1 , wherein the conductive element is included in a single build-up layer.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Liu Yueli

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/095

  of vias therein · CPC title