Method for manufacturing semiconductor device with a barrier layer having overhung portions

Patent metadata

Field	Value
Publication number	US-9502303-B2
Application number	US-201514682265-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Apr 9, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate with an insulation formed thereon, the insulation having plural trenches, and the adjacent trenches being spaced apart from each other;
forming a barrier layer on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprising overhung portions corresponding to the trenches;
forming a conductive seed layer on the barrier layer;
a step of completely removing an upper portion of the seed layer formed on an upper surface of the barrier layer;
a step of completely removing an upper portion of the barrier layer for exposing the upper surface of the insulation; and
after complete removals of the upper portions of the seed layer and the barrier layer, depositing conductors along the seed layer within the trenches for filling up the trenches, wherein top surfaces of the conductors are substantially aligned with the upper surface of the insulation after deposition of said conductors.

2. The method according to claim 1 , wherein the top surfaces of the conductors are substantially aligned with a top surface of the seed layer and a top surface of the barrier layer after depositing the conductors.

3. The method according to claim 1 , wherein a top surface of the seed layer is substantially aligned with a top surface of the barrier layer and substantially aligned with the upper surface of the insulation after removing the upper portion of the barrier layer.

4. The method according to claim 1 , wherein the act of removing the upper portion of the barrier layer for exposing the upper surface of the insulation comprises removing the overhung portions of the barrier layer.

5. The method according to claim 1 , wherein one of the trenches has a critical opening diameter (CD), and the overhung portions of the barrier layer correspondingly positioned in said trench has a size equal to or larger than half of the critical opening diameter (½*(CD)).

6. The method according to claim 1 , wherein the trenches are closed by the seed layer after forming the seed layer on the barrier layer with the overhung portions.

7. The method according to claim 1 , wherein after forming the seed layer on the barrier layer, openings of the trenches are sealed by the seed layer, and there are air holes respectively formed in the trenches and under the sealed openings of the trenches.

8. The method according to claim 1 , wherein the upper portion of the seed layer is removed by etching.

9. The method according to claim 8 , wherein the upper portion of the seed layer is etched by a ratio of an etching rate of the seed layer to an etching rate of the barrier layer, and said ratio is larger than 10.

10. The method according to claim 1 , wherein the upper portion and the overhung portions of the barrier layer are removed by dry etching.

11. The method according to claim 10 , wherein the upper portion of the barrier layer is dry etched by a ratio of an etching rate of the barrier layer to an etching rate of the seed layer, and said ratio is larger than 10.

12. The method according to claim 1 , wherein the seed layer is a tungsten seed layer, and the conductors are tungsten.

13. The method according to claim 1 , wherein the trenches are contact openings, and the conductors filling up the trenches are contact plugs.

14. The method according to claim 1 , wherein the substrate has a first area with plural first metal gates and a second area with plural second metal gates, and the adjacent first metal gates and the adjacent second metal gates are separated by the insulation.

15. The method according to claim 14 , wherein the insulation comprises:
spacers, formed at sidewalls of the first and second metal gates;
a contact etch stop layer (CESL), formed at outsides of the spacers; and
a patterned inter-layer dielectric layer (ILD), formed between each space of adjacent portions of the CESL.

16. The method according to claim 15 , wherein the insulation comprises:
a first inter-layer dielectric layer (ILD 1 ) on the substrate for separating the adjacent first metal gates and the adjacent second metal gates; and
a second inter-layer dielectric layer (ILD 2 ) formed on the first dielectric layer,
wherein the trenches penetrate the second inter-layer dielectric layer and the first inter-layer dielectric layer.

17. The method according to claim 16 , wherein the substrate further comprises plural fins for electrically connecting the first metal gates and second metal gates, wherein the trenches expose top surfaces of the fins.

18. The method according to claim 1 , wherein the barrier layer is formed by ion metal plasma (IMP) deposition.

19. The method according to claim 1 , wherein the substrate having the trenches filled with the conductors is subjected to a post-clean treatment.

Assignees

• United Microelectronics Corp

Inventors

• Li Kun-Ju
• Hung Kuo-Chin
• Huang Po-Cheng
• Li Yu-Ting
• Sie Wu-Sian
• Lu Chun-Tsen
• Lin Wen-Chin
• Tsai Fu-Shou

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title