Resistive memory device, operating method thereof, and system having the same

Patent metadata

Field	Value
Publication number	US-9502105-B2
Application number	US-201414199723-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Oct 23, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address signal and selecting the resistive memory cells, a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array, a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder and a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation in response to a write command and a plurality of write data.

First claim

What is claimed is:

1. A resistive memory device comprising:
a memory cell array comprising a plurality of resistive memory cells;
an address decoder suitable for decoding an address signal and selecting the resistive memory cells;
a read/write control circuit suitable for programming data to the memory cell array or reading data from the memory cell array;
a voltage generator suitable for generating operation voltages and providing the operation voltages to the address decoder; and
a controller suitable for controlling the address decoder, the read/write control circuit, and the voltage generator to perform a write operation for target memory cells in response to a write command and a plurality of write data,
wherein, while the controller waits after programming one memory cell of the target memory cells, the controller performs a program operation for another memory cell of the target memory cells, and then performs verification operations, for verifying whether the programmed target memory cells are in target resistance levels, on the programmed target memory cells in accordance with programmed sequence of the target memory cells when all the plurality of write data are programmed in the target memory cells.

2. The resistive memory device according to claim 1 , wherein a verify operation for one of the programmed memory cells is performed after verify operations are performed for memory cells programmed before the memory cell and before verify operations are performed for memory cells programmed after the memory cell.

3. The resistive memory device according to claim 1 , wherein the controller divides the plurality of write data into one or more data groups, performs the write operation for memory cells of a first data group, and repeats the write operation for the data groups by the number of data groups.

4. The resistive memory device according to claim 1 , wherein the resistive memory cell comprises a memory cell of which resistance increases after the memory cell is programmed.

5. The resistive memory device according to claim 1 , wherein the resistive memory cell comprises a phase change memory cell.

6. The resistive memory device according to claim 1 , wherein the resistive memory cell comprises a memory cell to store two or more bits of data.

7. A processor comprising:
a control unit suitable for generating a control signal in response to a command signal;
a calculation unit suitable for performing an operation on data in response to the control signal; and
a storage unit comprising a memory cell array having a plurality of resistive memory cells and a controller suitable for performing a write operation to store the data for target memory cells in response to the control signal,
wherein, while the controller waits after programming one memory cell of the target memory cells, the controller performs a program operation for another memory cell of the target memory cells, and then performs verification operations, for verifying whether the programmed target memory cells are in target resistance levels, on the programmed target memory cells in accordance with programmed sequence of the target memory cells when all the data are programmed in the target memory cells.

8. The processor according to claim 7 , wherein the controller divides the data into one or more data groups, performs the write operation for memory cells of a first data group, and repeats the write operation for the data groups by the number of data groups.

9. A data processing system comprising:
a main controller suitable for decoding a command inputted from an external device to output a control signal;
an interface suitable for exchanging the command and data between the external device and the main controller;
a main memory device suitable for storing applications, control signals, and the data; and
an auxiliary memory device suitable for storing program codes or the data,
wherein at least one of the main memory device and the auxiliary memory device comprises a memory cell array having a plurality of resistive memory cells and a controller suitable for performing a write operation to store the data for target memory cells in response to the control signal, and
wherein, while the controller waits after programming one memory cell of the target memory cells, the controller performs a program operation for another memory cell of the target memory cells, and then performs verification operations, for verifying whether the programmed target memory cells are in target resistance levels, on the programmed target memory cells in accordance with programmed sequence of the target memory cells when all the data are programmed in the target memory cells.

10. The data processing system according to claim 9 , wherein the controller divides the data into one or more data groups, performs the write operation for memory cells of a first data group, and repeats the write operation for the data groups by the number of data groups.

11. The data processing system according to claim 9 , wherein the interface comprises one of a man-machine interface device, a card interface device, and a disk interface device.

12. An electronic system comprising:
a resistive memory device comprises a memory cell array having a plurality of resistive memory cells and a controller suitable for performing a write operation for target memory cells in response to a write command and a plurality of write data; and
a memory controller suitable for accessing the resistive memory device by generating the write command and the plurality of write data in response to a request of an external device,
wherein, while the controller waits after programming one memory cell of the target memory cells, the controller performs a program operation for another memory cell of the target memory cells, and then performs verification operations, for verifying whether the programmed target memory cells are in target resistance levels, on the programmed target memory cells in accordance with programmed sequence of the target memory cells when all the plurality of write data are programmed in the target memory cells.

13. The electronic system according to claim 12 , wherein the controller divides the plurality of write data into one or more data groups, performs the write operation for memory cells of a first data group, and repeats the write operation for the data groups by the number of data groups.

14. The electronic system according to claim 12 , wherein the memory controller comprises:
a processor suitable for decoding a command from a host as the external device;
a working memory suitable for storing applications, data, and control signals used for operating the memory controller;
a host interface suitable for performing protocol conversion for exchanging data and control signals between the host and the memory controller; and
a memory interface suitable for performing protocol conversion for exchanging data and signals between the memory controller and the resistive memory device.

15. The electronic system according to claim 12 , wherein the memory controller comprises:
a processor suitable for decoding a command inputted from the external device;
a working memory suitable for storing applications, data, and control signals used for operating the processor; and
a user interface suitable for providing a data input/output environment between the processor and the external device.

16. The electronic system according to claim 15 , further comprising a communication module suitable for accessing a wired or wireless communication network.

17.

Assignees

• Sk Hynix Inc

Inventors

• Cheon Jun Ho

Classifications

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0064

  Verifying circuits or methods · CPC title

• G11C13/02

  using elements whose operation depends upon chemical change {(G11C13/0009 takes precedence)} · CPC title