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US-2024274171-A1 · Aug 15, 2024 · US
Method of operating a voltage regulator to reduce contention current
US9502098B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502098-B2 |
| Application number | US-201615014119-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 3, 2016 |
| Priority date | Jun 22, 2010 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of operating a first voltage regulator, the method comprising: electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage; and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array, wherein the first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a…
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- G11C5/147Primary
Physics · mapped topic
- G11C11/4074Primary
Physics · mapped topic
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- What does patent US9502098B2 cover?
- A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C5/147. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).