Printed circuit board and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9497853-B2
Application number	US-201113997544-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 24, 2010
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

First claim

The invention claimed is:

1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer under the first insulating layer;
a metal substrate buried in the first insulating layer and the second insulating layer and including a first region and a second region; and
an outer circuit layer on a top surface of the first insulating layer or a bottom surface of the second insulating layer;
wherein the metal substrate comprises:
at least one via formed through the first and second insulating layers and disposed in the first region of the metal substrate;
an inner circuit layer buried in the first and second insulating layers and disposed in the second region of the metal substrate; and
an adhesive layer formed on the top surface of the first insulating layer or the bottom surface of the second insulating layer to expose the via;
wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the first and second insulating layers, and the first width is larger than the second width;
wherein the inner circuit layer comprises:
a first circuit part buried in the first insulating layer; and
a second circuit part buried in the second insulating layer;
wherein a top surface of the via is exposed through the top surface of the first insulating layer, and a bottom surface of the via is exposed through the bottom surface of the second insulating layer; and
wherein a sectional shape of the via is different from a sectional shape of the inner circuit layer.

2. The printed circuit board of claim 1 , wherein an upper portion of the via from a center part of the via is buried in the first insulating layer; and
wherein a lower portion of the via from the center part of the via is buried in the second insulating layer.

3. The printed circuit board of claim 2 , wherein the first and second circuit parts of the inner circuit layer are symmetrically formed about a boundary between the first and second insulating layers.

4. The printed circuit board of claim 1 , wherein the first circuit part or the second circuit part of the inner circuit layer has a triangular sectional shape.

5. The printed circuit board of claim 1 , wherein the first and second circuit parts of the inner circuit layer have a lozenge sectional shape that is symmetrically formed about a boundary between the first and second insulating layers.

6. The printed circuit board of claim 1 , wherein the via and the inner circuit layer are formed by using a same material.

7. The printed circuit board of claim 1 , wherein the via has a hexagonal sectional shape.

8. The printed circuit board of claim 1 , wherein the outer circuit layer is filled in a pattern groove formed on the top surface of the first insulating layer or the bottom surface of the second insulating layer.

9. The printed circuit board of claim 8 , wherein the pattern groove has a U-sectional shape.

10. The printed circuit board of claim 1 , wherein the adhesive layer includes primer resin.

11. A method for manufacturing a printed circuit board, the method comprising:
forming at least one via and an inner circuit layer by etching a metal substrate;
forming an insulating layer to bury the via; and
forming an outer circuit layer on a top surface or a bottom surface of the insulating layer, wherein the forming of the via and the inner circuit layer comprises:
forming a first part of the via and a first circuit part of the inner circuit layer by etching an upper portion of the metal substrate;
forming a first insulating layer to bury the first part of the via and the first circuit part of the inner circuit layer; and
forming a second part of the via below the first part of the via and a second circuit part of the inner circuit layer below the first circuit part of the inner circuit layer by etching a lower portion of the metal substrate;
wherein the first circuit part of the inner circuit layer is formed with the first part of the via by using the metal substrate and the second circuit part of the inner circuit layer is formed with the second part of the via by using the metal substrate;
wherein a top surface of the via is exposed through a top surface of the first insulating layer, and a bottom surface of the via is exposed through a bottom surface of a second insulating layer;
wherein a sectional shape of the via is different from a sectional shape of the inner circuit layer; and
wherein the forming of the first part of the via comprises:
simultaneously forming the first part of the via and the first circuit part of the inner circuit layer such that the first circuit art of the inner circuit layer has a triangular sectional shape by wet-etching the metal substrate.

12. The method of claim 11 ,
wherein the first and second circuit parts of the inner circuit layer are symmetrically formed about a boundary between the first and second insulating layers.

13. The method of claim 11 , wherein the forming of the outer circuit layer comprises:
forming a copper foil layer on and under the insulating layer;
forming a photoresist pattern on the copper foil layer; and
forming the outer circuit layer by etching the copper foil layer using the photoresist pattern as a mask.

14. The method of claim 11 , wherein a width of a boundary between the first and second parts of the via is larger than a width of a boundary between the via and the insulating layer.

15. The method of claim 11 , wherein the forming of the outer circuit layer comprises:
forming a pattern groove on a top surface or a bottom surface of the insulating layer; and
filling the pattern groove with a conductive material by plating the conductive material.

Assignees

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do
• Lg Innotek Co Ltd

Inventors

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do

Classifications

• H05K2203/0376

  Etching temporary metallic carrier substrate · CPC title

• H05K3/4652

  Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence) · CPC title

• H05K2201/098

  Special shape of the cross-section of conductors, e.g. very thick plated conductors · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K1/0298 Primary

  Multilayer circuits · CPC title