Mechanism for forming metal gate structure

Patent metadata

Field	Value
Publication number	US-9496367-B2
Application number	US-201514978167-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Oct 30, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising: providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate, wherein a source region and a drain region are formed in the semiconductor substrate, the metal gate stack is between the source region and the drain region, and the insulating layer surrounds the metal gate stack; forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively; performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings; and after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings, wherein the dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively; after the formation of the dielectric spacer liner layer, performing a second pre-amorphized implantation process to increase a thickness of the amorphous regions.

2. The method for forming a semiconductor device as claimed in claim 1 , further comprising: after the second pre-amorphized implantation process, performing a salicidation process to turn the amorphous regions into metal silicide regions.

3. The method for forming a semiconductor device as claimed in claim 2 , further comprising:
forming contact plugs in the contact openings to electrically connect to the metal silicide regions.

4. The method for forming a semiconductor device as claimed in claim 2 , wherein a width of the metal silicide region is larger than a diameter of the contact opening.

5. The method for forming a semiconductor device as claimed in claim 1 , further comprising:
performing a salicidation process to turn the amorphous regions into metal silicide regions.

6. The method for forming a semiconductor device as claimed in claim 1 , wherein a width of the amorphous region is larger than a diameter of the contact opening.

7. The method for forming a semiconductor device as claimed in claim 1 , wherein an implantation angle of the first pre-amorphized implantation process ranges from about 0° to about 30°, and the implantation angle is relative to a normal line of a top surface of the amorphous region.

8. A method for forming a semiconductor device, comprising: providing a semiconductor substrate, a metal gate stack, stressors, and an insulating layer formed over the semiconductor substrate, wherein a source region and a drain region are formed in the semiconductor substrate, the metal gate stack is between the source region and the drain region, the stressors are formed in the source region and the drain region, respectively, and the insulating layer surrounds the metal gate stack and covers the stressors; forming contact openings passing through the insulating layer to expose the stressors, respectively; performing a first pre-amorphized implantation process to form amorphous regions in the stressors exposed by the contact openings; and after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings, wherein the dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively; after the formation of the dielectric spacer liner layer, performing a second pre-amorphized implantation process to increase a thickness of the amorphous regions.

9. The method for forming a semiconductor device as claimed in claim 8 , further comprising: after the second pre-amorphized implantation process, performing a salicidation process to turn the amorphous regions into metal silicide regions.

10. The method for forming a semiconductor device as claimed in claim 9 , further comprising:
forming contact plugs in the contact openings to electrically connect to the metal silicide regions.

11. The method for forming a semiconductor device as claimed in claim 8 , wherein a width of the amorphous region is greater than the thickness of the amorphous region.

12. The method for forming a semiconductor device as claimed in claim 8 , further comprising:
performing a salicidation process to turn the amorphous regions into metal silicide regions.

13. A method for forming a semiconductor device, comprising: providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate, wherein a source region and a drain region are formed in the semiconductor substrate, the metal gate stack is between the source region and the drain region, and the insulating layer surrounds the metal gate stack; forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively; performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings, wherein a first pre-amorphized implantation element is implanted in the amorphous regions and the insulating layer adjacent to the contact openings; and after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings, wherein the dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively after the formation of the dielectric spacer liner layer, performing a second pre-amorphized implantation process to increase a thickness of the amorphous regions, wherein a second pre-amorphized implantation element is implanted in the amorphous regions and the dielectric spacer liner layer.

14. The method for forming a semiconductor device as claimed in claim 13 , wherein an implantation angle of the first pre-amorphized implantation process ranges from about 0° to about 30°, and the implantation angle is relative to a normal line of a top surface of the amorphous region.

15. The method for forming a semiconductor device as claimed in claim 13 , wherein an implantation angle of the second pre-amorphized implantation process ranges from about 0° to about 30°, and the implantation angle is relative to a normal line of a top surface of the amorphous region.

16. The method for forming a semiconductor device as claimed in claim 13 , wherein the dielectric spacer liner layer is in direct contact with the amorphous regions.

17. The method for forming a semiconductor device as claimed in claim 13 , wherein a width of the amorphous region is larger than a diameter of the contact opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Tien-Chun
• Lo Yi-Chun
• Chang Chia-Der
• Chi Guo-Chiang
• Lo Chia-Ping
• Yang Fu-Kai
• Hsu Hung-Chang
• Wang Mei-Yun

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10P30/225

  of a molecular ion, e.g. decaborane · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title