Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axis

Patent metadata

Field	Value
Publication number	US-9496243-B2
Application number	US-201615069131-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Oct 3, 2011
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a circuit panel having first and second opposed surfaces and first and second panel contacts at the first and second surfaces, respectively; and
a first microelectronic package having a plurality of terminals mounted to the first panel contacts,
a second microelectronic package having a plurality of terminals mounted to the second panel contacts,
each of the first and second microelectronic packages including:
a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon;
a microelectronic element having memory storage array function, the microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face,
the plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the plurality of terminals electrically coupled with the substrate contacts and including first terminals disposed at locations within first and second sets, each set of first terminals distributed at at least eight different positions within a column of at least one column extending in a first direction, the first terminals of each of the first and second sets being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element,
wherein the signal assignments of the first terminals in the first set are symmetric about an axis extending in the first direction with the signal assignments of the first terminals in the second set,
the terminals further including first and second groups of second terminals, each of the first and second groups of second terminals having at least eight data terminals disposed on first and second opposite sides of the axis, respectively,
wherein each group of the second terminals being distributed at at least four different positions within a row of at least one row extending in a second direction transverse to the first direction, and each of the data terminals of the first and second groups is configured to carry a data signal for read and write access to locations of a memory storage array within the microelectronic element, and each data terminal of the first group has modulo-X symmetry about the axis with each data terminals of the second group, wherein X is a whole number greater than 2.

2. The microelectronic assembly as claimed in claim 1 , wherein X is equal to 8.

3. The microelectronic assembly as claimed in claim 1 , wherein X is equal to N times 8, wherein N is a whole number greater than one.

4. The microelectronic assembly as claimed in claim 1 , wherein X is equal to 2n, wherein n is greater than or equal to two.

5. The microelectronic assembly as claimed in claim 1 , wherein each group of second terminals includes a data strobe terminal, wherein the signal class assignment of each data strobe terminal in the first group is symmetric about the axis with the signal class assignment of a corresponding data strobe terminal in the second group.

6. The microelectronic assembly as claimed in claim 1 , wherein each group of second terminals includes a data mask terminal, wherein the signal class assignment of each data mask terminal in the first group is symmetric about the axis with the signal class assignment of a corresponding mask terminal in the second group.

7. The microelectronic assembly as claimed in claim 1 , wherein the first terminals of the second set of the first microelectronic package are connected through the circuit panel to the first terminals of the first set of the second microelectronic package, each first terminal of the second set of the first microelectronic package being aligned within one ball pitch of the corresponding first terminal to which it is are electrically coupled of the first set of the second microelectronic package in x and y orthogonal directions parallel to the first and second surfaces of the circuit panel.

8. The microelectronic assembly as claimed in claim 7 , wherein the second set of the first microelectronic package and the first set of the second microelectronic package are aligned with one another in the x and y orthogonal directions such that the terminals of the second set of the first microelectronic package and the first set of the second microelectronic package are coincident with one another.

9. The microelectronic assembly as claimed in claim 7 , wherein a length of a stub of at least one of electrical connections between one of the first terminals of the first microelectronic package and a corresponding one of the first terminals of the second microelectronic package coupled to such first terminal of the first microelectronic package is less than seven times a minimum pitch of the first terminals of each of the microelectronic packages.

10. The microelectronic assembly of claim 9 , wherein the total combined length of conductive elements connecting a pair of electrically coupled first and second panel contacts exposed at the first and second surfaces of the circuit panel is less than seven times a smallest pitch of the panel contacts.

11. The microelectronic assembly as claimed in claim 7 , wherein at least some of the electrical connections through the circuit panel between the first terminals of the first microelectronic package and the first terminals of the second microelectronic package have an electrical length of approximately a thickness of the circuit panel.

12. The microelectronic assembly as claimed in claim 7 , wherein each set of first terminals of each microelectronic package has two parallel columns, and wherein the circuit panel includes no more than two routing layers for global routing of all of the address information between respective connection sites on the circuit panel at which the first terminals of one or more of the microelectronic packages are electrically connected.

13. A microelectronic package, comprising:
a substrate having first and second opposed surfaces, the first surface having substrate contacts thereon;
a microelectronic element having a rear face facing the first surface, a front face opposite the rear face, and contacts on the front face electrically connected with the substrate contacts through conductive structure extending above the front face;
a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the plurality of terminals electrically coupled with the substrate contacts and including first terminals disposed at locations within first and second sets, each set of first terminals distributed at at least eight different positions within a column of at least one column extending in a first direction, the first terminals of each of the first and second sets being configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element,
wherein the signal assignments of the first terminals in the first set are symmetric about an axis extending in the first direction with the signal assignments of the first terminals in the second set,
the terminals further including first and second groups of second terminals, each of the first and second groups o

Assignees

• Invensas Corp

Inventors

• Crisp Richard Dewitt
• Zohni Wael
• Haba Belgacem
• Lambrecht Frank

Classifications

• G11C5/066

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title