Apparatus and method for performing a permute operation

Patent metadata

Field	Value
Publication number	US-9495162-B2
Application number	US-201113996072-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from the destination operand and a second source operand based on index values stored in a first source operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand; if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.

First claim

We claim:

1. A processor comprising:
non-transitory machine-readable medium including an instruction including a first source operand, a second source operand, and a destination operand, the instruction when executed by the processor, causing the processor to perform:
reading values from a mask data structure to determine whether masking is implemented for each data element of the destination operand;
if masking is not implemented for a particular data element, then selecting one data element from the destination operand and the second source operand based on an index value of a plurality of index values stored in the first source operand to be copied to a data element position for that particular data element within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand based on the plurality of index values;
if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element, wherein the designated masking operation comprises leaving current bit values stored in the particular data element unchanged.

2. The processor as in claim 1 wherein the destination operand and the first and second source operands are each 128-bits in length.

3. The processor as in claim 2 wherein the data elements are each 32-bits in length.

4. The processor as in claim 2 wherein the data elements are each 16-bits in length.

5. The processor as in claim 2 wherein the data elements are each 64-bits in length.

6. A method for permuting data elements with masking comprising:
reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand;
if masking is not implemented for a particular data element, then selecting one data element form the destination operand and a second source operand based on an index value out of a plurality of index values stored in a first source operand to be copied to a data element position for that particular data element within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand based on the plurality of index values;
if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with response to that particular data element, wherein the designated masking operation comprises leaving current bit values stored in the particular data element unchanged.

7. The method as in claim 6 wherein the destination operand and the first and second source operands are each 128-bits in length.

8. The method as in claim 7 wherein the data elements are each 32-bits in length.

9. The method as in claim 7 wherein the data elements are each 16-bits in length.

10. The method as in claim 7 wherein the data elements are each 64-bits in length.

11. A computer system to perform permutation operations with masking comprising:
a memory for storing program code; and
a processor for processing the program code to perform the operations of:
reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand;
if masking is not implemented for a particular data element, then selecting one data element from the destination operand and a second source operand based on an index value out of a plurality of index values stored in a first source operand to be copied to a data element position for that particular data element within the destination operand, wherein any one of the data elements from either the destination operand and the second source operand may be copied to any one of the data element positions within the destination operand based on the plurality of index values;
if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element, wherein the designated masking operation comprises leaving current bit values stored in the particular data element unchanged.

12. The system as in claim 11 wherein the destination operand and the first and second source operands are each 128-bits in length.

13. The system in claim 12 wherein the data elements are each 32-bits in length.

14. The system in claim 12 wherein the data elements are each 16-bits in length.

15. The system in claim 12 wherein the data elements are each 64-bits in length.

16. The system in claim 11 further comprising:
a display adapter to render graphics images in response to execution of the program code by the processor.

17. The system as in claim 16 further comprising:
a user input interface to receive control signals from a user input device, the processor executing the program code in response to the control signals.

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Valentine Robert
• Hagog Mostafa
• Corbal Jesus
• Uliel Tal
• Sperber Zeev
• Gradstein Amit
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Valentine Robert
• Hagog Mostafa
• Corbal Jesus
• Uliel Tal
• Sperber Zeev
• Gradstein Amit

Classifications

• G06F9/30196 Primary

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30038

  using a mask · CPC title