Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

Patent metadata

Field	Value
Publication number	US-9182983-B2
Application number	US-201213730839-A
Country	US
Kind code	B2
Filing date	Dec 29, 2012
Priority date	Dec 2, 1994
Publication date	Nov 10, 2015
Grant date	Nov 10, 2015

Abstract

A processor of an aspect includes a register file including a first register to hold a first packed data including a first low data element and a first high data element, a second register to hold a second packed data including a second low data element and a second high data element, and a third register. The processor also includes a decoder to decode an unpack instruction. The processor also includes a functional unit coupled with the decoder and the register file. The functional unit, in response to the decoder decoding the unpack instruction, is to transfer the first low data element to a high position of the third register and the second low data element to a low position of the third register.

First claim

What is claimed is:

1. A system comprising:
a processing system to support: 2D/3D graphics, image processing, video compression, video decompression, and audio manipulation; wherein the processing system is further to be coupled with a display device and is to be coupled with an input device, the processing system comprising a processor including:
a register file including a first register to hold a first packed data including a first low data element and a first high data element, a second register to hold a second packed data including a second low data element and a second high data element, a third register, and a fourth register;
a decoder to decode an unpack instruction, and a pack instruction; and
at least one functional unit coupled with the decoder and the register file, the at least one functional unit, in response to the decoder decoding the unpack instruction to store the first low data element to a high position of the third register and the second low data element to a low position of the third register,
the at least one functional unit, in response to the decoder decoding the pack instruction, to pack all source data elements with saturation when appropriate into a result packed data.

2. The system of claim 1 , wherein the first, second and third registers are each to hold at least 32 bits.

3. A method comprising:
accessing a first packed data including a first low data element and a first high data element in a first register;
accessing a second packed data including a second low data element and a second high data element in a second register;
decoding an unpack instruction;
in response to the decoding the unpack instruction, storing the first low data element to a high position of a third register and the second low data element to a low position of the third register;
decoding a pack instruction indicating a fourth register and a fifth register;
in response to decoding the pack instruction packing and saturating when appropriate all data elements from the fourth register in a lowest order half of a result.

4. The method of claim 3 , wherein the first, second, and third registers are each to hold at least 32 bits.

5. The method of claim 3 , wherein the first, second, and third registers are included in a processor of a processing system to support: 2D/3D graphics, image processing, video compression, video decompression, and audio manipulation; wherein the processing system is further to be coupled with a display device and to be coupled with an input device.

6. A computer readable medium including code having an unpack instruction and a pack instruction, the code when executed to cause a machine to perform operations comprising:
access a first packed data including a first low data element and a first high data element in a first register;
access a second packed data including a second low data element and a second high data element in a second register;
decode the unpack instruction;
in response to the decoding of the unpack instruction, store the first low data element to a high position of a third register and the second low data element to a low position of the third register;
decoding the pack instruction indicating a fourth register and a fifth register;
in response to decoding the pack instruction packing and saturating when appropriate all data elements from the fourth register in a lowest order half of a result.

7. The computer readable medium of claim 6 , wherein the first, second, and third registers are each to hold at least 32 bits.

8. The computer readable medium of claim 6 , wherein the first, second, and third registers are included in a processor of a processing system to support: 2D/3D graphics, image processing, video compression, video decompression, and audio manipulation; wherein the processing system is further to be coupled with a display device and to be coupled with an input device.

Assignees

• Intel Corp

Inventors

• Peleg Alexander D
• Yaari Yaakov
• Mittal Millind
• Mennemeier Larry M
• Eitan Benny

Classifications

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title

• G06F9/30109

  having multiple operands in a single register · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title