CDR voter with improved frequency offset tolerance

Patent metadata

Field	Value
Publication number	US-9490968-B2
Application number	US-201414192100-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Feb 27, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.

First claim

What is claimed is:

1. A circuit comprising:
a voter having one or more voter inputs, the voter generating, for each given voter input, an up vote indicative of a recovered clock having a negative phase offset relative to the given voter input, or a down vote indicative of the recovered clock having a positive phase offset relative to the given voter input;
a comparator coupled to the voter, the comparator configured to output a phase adjustment signal and a tie signal based upon the up and down votes generated;
a shift register;
a multiplexer coupled to the comparator and the shift register, the multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output, based on the tie signal; and
a flip-flop receiving the multiplexer output at a data input of the flip-flop, the flip-flop generating a phase adjustment output signal, the shift register receiving the phase adjustment output signal directly from the flip-flop at a data input of the shift register.

2. The circuit of claim 1 , wherein the shift register includes two or more flip-flops.

3. The circuit of claim 1 , wherein the voter includes two or more voter inputs.

4. The circuit of claim 1 , wherein the shift register includes at least as many flip-flops as a number of the one or more voter inputs.

5. The circuit of claim 1 , wherein the shift register includes at least twice as many flip-flops as a number of the one or more voter inputs.

6. The circuit of claim 1 , wherein the shift register includes at least as many flip-flops as a number of received consecutive identical values at a given voter input.

7. The circuit of claim 1 , wherein the one or more voter inputs comprise one or more data inputs and one or more edge inputs.

8. A circuit comprising:
a shift register;
a multiplexer configured to select either a phase adjustment signal or an output from the shift register, as a multiplexer output based upon a tie signal; and
a flip-flop receiving the multiplexer output at a data input of the flip-flop, the flip-flop generating a phase adjustment output signal, the shift register receiving the phase adjustment output signal directly from the flip-flop at a data input of the shift register.

9. The circuit of claim 8 , further comprising a voting module having one or more voter inputs, the voting module generating the tie signal and the phase adjustment signal based upon a majority vote of phase offset for the one or more voter inputs relative to a recovered clock.

10. The circuit of claim 8 , wherein the shift register includes two or more flip-flops.

11. The circuit of claim 9 , wherein the voting module includes two or more voter inputs.

12. The circuit of claim 9 , wherein the shift register includes at least as many flip-flops as a number of the one or more voter inputs.

13. The circuit of claim 9 , wherein the shift register includes at least twice as many flip-flops as a number of the one or more voter inputs.

14. The circuit of claim 9 , wherein the shift register includes at least as many flip-flops as a number of received consecutive identical values at a given voter input.

15. The circuit of claim 9 , wherein the one or more voter inputs comprise one or more data inputs and one or more edge inputs.

16. A method comprising:
selecting, at a multiplexer, either a phase adjustment signal or an output from a shift register, as a multiplexer output based upon a tie signal; and
receiving, at a flip-flop, the multiplexer output at a data input of the flip-flop, the flip-flop generating a phase adjustment output signal, the shift register receiving the phase adjustment output signal directly from the flip-flop at a data input of the shift register.

17. The method of claim 16 , further comprising generating, at a voting module, the tie signal and the phase adjustment signal based upon a majority vote of phase offset for the one or more voter inputs of the voting module relative to a recovered clock.

18. The method of claim 16 , wherein the shift register includes two or more flip-flops.

19. The method of claim 17 , wherein the shift register includes at least as many flip-flops as a number of the one or more voter inputs.

20. The method of claim 17 , wherein the one or more voter inputs comprise one or more data inputs and one or more edge inputs.

21. The method of claim 17 , wherein the shift register includes at least as many flip-flops as a number of received consecutive identical values at a given voter input.

22. A method comprising:
receiving bit transition information for one or more bits;
determining whether to increment, decrement, or keep unchanged a phase relationship of a phase interpolator, based upon the bit transition information;
generating a phase adjustment output, based upon the determination; and
storing one or more sequential values of the phase adjustment output, the phase adjustment output generated directly from the stored sequential values of the phase adjustment output when the phase relationship is determined as unchanged;
wherein the phase relationship determined as kept unchanged is indicative of a recovered clock being locked to the bit transition information and indicative of the bit transition information being unavailable.

Assignees

• Cavium Inc

Inventors

• Crain Ethan

Classifications

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title