Frequency planning for digital power amplifier

Patent metadata

Field	Value
Publication number	US-9490966-B2
Application number	US-201514977547-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Dec 4, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, an apparatus including: processor electronics; transceiver electronics coupled with the processor electronics, the transceiver electronics including modulation circuitry and a digital power amplifier coupled with the modulation circuitry; a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency; a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and one or more antennas coupled with the digital power amplifier in the transceiver electronics; wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.

First claim

What is claimed is:

1. An apparatus comprising:
processor electronics;
transceiver electronics coupled with the processor electronics, the transceiver electronics comprising modulation circuitry and a digital power amplifier coupled with the modulation circuitry;
a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency;
a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and
one or more antennas coupled with the digital power amplifier in the transceiver electronics;
wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and
wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.

2. The apparatus of claim 1 , wherein the local oscillator frequency is equal to the sampling clock frequency.

3. The apparatus of claim 1 , wherein the local oscillator frequency is two times the sampling clock frequency.

4. The apparatus of claim 1 , wherein the clock source is also coupled with the processor electronics to distribute a common clock signal to at least one processing unit of the processor electronics and to the digital power amplifier.

5. The apparatus of claim 1 , wherein the digital power amplifier is a Polar digital power amplifier.

6. The apparatus of claim 1 , wherein the digital power amplifier is an IQ/Cartesian digital power amplifier.

7. The apparatus of claim 1 , wherein the digital power amplifier comprises multiple segments, each of the multiple segments comprising a latch, an AND gate, and an amplifier circuit.

8. A method comprising:
upconverting a baseband signal from processor electronics using a local oscillator signal from a local oscillator, which has a local oscillator frequency, to generate a transmission signal in transceiver electronics;
feeding the transmission signal to a digital power amplifier associated with the transceiver electronics;
sampling the transmission signal in the digital power amplifier using a clock signal from a clock source, which has a clock frequency, to generate a sampled transmission signal;
amplifying the sampled transmission signal in the digital power amplifier to generate an amplified output signal; and
transmitting the output signal using one or more antennas coupled with the digital power amplifier associated with the transceiver electronics;
wherein the local oscillator frequency is an integer multiple of the clock frequency; and
wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.

9. The method of claim 8 , wherein the local oscillator frequency is equal to the clock frequency.

10. The method of claim 8 , wherein the local oscillator frequency is two times the clock frequency.

11. The method of claim 8 , comprising distributing a single clock signal to both (i) a baseband processing unit in the processor electronics for generating the baseband signal and (ii) the digital power amplifier for the sampling.

12. The method of claim 8 , comprising phase modulating the transmission signal before feeding the transmission signal to multiple, respective segments of the digital power amplifier.

13. The method of claim 8 , wherein the feeding comprises feeding the transmission signal to separate I and Q banks of the digital power amplifier.

14. The method of claim 8 , wherein the digital power amplifier comprises multiple segments, each of the multiple segments comprising a latch, an AND gate, and an amplifier circuit.

Assignees

• Marvell World Trade Ltd

Inventors

• Winoto Renaldi

Classifications

• H04B2001/0408

  with power amplifiers · CPC title

• H04L7/02 Primary

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H03F3/2175

  using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title

• H04B1/04 Primary

  Circuits · CPC title

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title