Reception circuit

Patent metadata

Field	Value
Publication number	US-9112673-B2
Application number	US-201414334761-A
Country	US
Kind code	B2
Filing date	Jul 18, 2014
Priority date	Aug 9, 2013
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector.

First claim

What is claimed is:

1. A reception circuit comprising:
a phase detector that detects a phase code based on a phase of data in relation to a first clock signal;
a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes;
a calibrator that, in the calibration mode, stores a difference between the phase code detected by the phase detector and an ideal value of…

Assignees

• Fujitsu Ltd

Inventors

• Suzuki Shigeto
• Tamura Hirotaka

Classifications

• H04L7/0025 Primary

  Electricity · mapped topic

• H04L7/02 Primary

  Electricity · mapped topic

• H04L7/0079

  Electricity · mapped topic

• H04B1/16

  Electricity · mapped topic

• H04L7/0331

  Electricity · mapped topic