Method of forming a semiconductor device termination and structure therefor

Patent metadata

Field	Value
Publication number	US-9490372-B2
Application number	US-201113227011-A
Country	US
Kind code	B2
Filing date	Sep 7, 2011
Priority date	Jan 21, 2011
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first layer of the first conductivity type formed overlying the semiconductor substrate, the first layer having a surface;
the semiconductor device including an active region and an edge termination area wherein the edge termination area is external to the active region; and
an edge termination structure within the edge termination area, the edge termination structure including:
a first region,
a second region, where the second region has a different conductivity type than the first region and where the second region is adjacent to the first region,
a first buffer region adjacent to the second region, the first buffer region having a length that extends in a first direction away from the surface of the first layer and having a width along the length wherein the first buffer region does not extend laterally in a second direction to overlie one of the first region or the second region;
a third region formed adjacent to the first buffer region wherein the third region is a semiconductor material, the third region having a first surface in a plane substantially parallel to the surface of the first layer and wherein the first buffer region is disposed between the second region and the third region, where the edge termination structure is adjacent to the first layer and where the edge termination structure overlies the semiconductor substrate; and
a dielectric layer on and in direct contact with the first surface of the third region, the dielectric layer extending onto and in direct contact with the second region.

2. The semiconductor device according to claim 1 , where the first region and the third region are N-type.

3. The semiconductor device according to claim 1 where the edge termination structure further comprises:
a fourth region, where the fourth region has a different conductivity type than the third region and where the fourth region is formed adjacent to the third region.

4. The semiconductor device according to claim 3 , where the first region is N-type and where the third region is P-type.

5. The semiconductor device according to claim 3 where the first buffer region comprises at least one of a gas region, or an insulating layer.

6. The semiconductor device according to claim 5 , where the first buffer region comprises an insulator having at least one void.

7. The semiconductor device according to claim 6 , where the at least one void includes air.

8. The semiconductor device according to claim 3 further comprising:
a first separator layer between the first region and the second region where the first separator layer is at least one of an intrinsic layer or a dielectric layer.

9. The semiconductor device according to claim 8 further comprising a second separator layer between the third region and the fourth region where the second separator layer is at least one of an intrinsic layer or a dielectric layer.

10. The semiconductor device according to claim 3 , where the first region is p-type, where the second region is n-type, where the third region is n-type, and where the fourth region is p-type.

11. The semiconductor device of claim 1 wherein the third region is substantially parallel to one of the first region or the second region.

12. The semiconductor device of claim 1 wherein the width of the first buffer region is substantially no greater than a width of another buffer region formed in the active area of the semiconductor device wherein an edge of the active area borders the termination area.

13. The semiconductor device of claim 1 wherein the first buffer region does not extend in a second direction for a second distance that is greater than the width wherein the second direction is substantially parallel to the semiconductor substrate.

14. The semiconductor device of claim 1 wherein the third region has the different conductivity type.

15. The semiconductor device of claim 1 wherein the edge termination area is adjacent to the active region and is disposed between the active region and an edge of the semiconductor device.

Assignees

• Guitart Jaume Roig
• Moens Peter
• Hossain Zia
• Semiconductor Components Ind Llc

Inventors

• Guitart Jaume Roig
• Moens Peter
• Hossain Zia

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/111

  Field plates · CPC title