Semiconductor transistor having a stressed channel

Patent metadata

Field	Value
Publication number	US-9490364-B2
Application number	US-65532909-A
Country	US
Kind code	B2
Filing date	Dec 29, 2009
Priority date	Nov 1, 2001
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases I DSAT and I DLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

First claim

The invention claimed is:

1. A transistor comprising:
a silicon layer disposed directly on a monocrystalline substrate, the silicon layer having a first lattice constant;
a silicon channel region disposed in said silicon layer;
a gate dielectric layer over the silicon channel region, wherein the gate dielectric layer includes an oxide and a nitride and is formed to a thickness of between 5 Angstroms and 30 Angstroms;
a gate electrode on the gate dielectric layer;
a pair of spacers on opposing sides of the gate electrode; and
source and drain regions on opposite sides of the silicon channel region and above a portion of said silicon layer, the source and drain regions each having a first portion comprising a boron doped portion of said silicon layer and a second portion above the first portion, the second portion comprising a boron doped epitaxial silicon germanium layer having a second lattice constant that is different than the first lattice constant of the silicon layer, wherein:
the second portion creates a compressive stress in the silicon channel region;
the first portion extends to a first depth below the second portion, which extends to a second depth, separating the second portion from the silicon layer; and
the first portion extends to a third depth, less than the second depth, beneath the pair of spacers and beneath a portion of the gate dielectric layer, separating the second portion from the channel region.

2. The transistor of claim 1 , wherein the gate dielectric comprises an oxynitride layer.

3. The transistor of claim 1 , further comprising a shallow trench isolation region adjacent to the source region or the drain region.

4. The transistor of claim 1 , wherein the silicon channel region further comprises an n-type dopant.

5. The transistor of claim 4 , wherein the silicon layer comprises the n-type dopant.

6. The transistor of claim 5 , wherein the silicon layer and channel region have the substantially the same n-type dopant concentration.

7. The transistor of claim 1 , wherein the n-type dopant comprises one or both of phosphorous and arsenic.

8. The transistor of claim 1 , wherein the boron dopant concentration in the first portion disposed below the spacers is less than the boron dopant in the second portion.

9. A transistor comprising:
a silicon layer disposed directly on a monocrystalline substrate, the silicon layer having a first lattice constant matching that of the substrate;
a silicon channel region disposed in said silicon layer;
a gate dielectric layer disposed over the silicon channel region and having a thickness of between 5 Angstroms and 30 Angstroms;
a gate electrode disposed over the gate dielectric layer;
a pair of dielectric spacers disposed on opposing sides of the gate electrode; and
source and drain regions disposed on opposite sides of the silicon channel region and disposed over a portion of said silicon layer, the source and drain regions each having a first portion comprising boron doped silicon separating the silicon layer from a second portion of the source and drain regions comprising a boron doped epitaxial silicon germanium layer having a second lattice constant that is different than the first lattice constant, wherein:
the second portion creates a compressive stress in the silicon channel region; and
the first portion extends to a depth less than that of the second portion within a region of the silicon layer beneath the pair of spacers and beneath a portion of the gate dielectric layer, laterally separating the second portion from the channel region.

10. The transistor of claim 9 , wherein the gate dielectric comprises and oxide and nitride.

11. The transistor of claim 9 , further comprising a shallow trench isolation region adjacent to the source region or the drain region.

12. The transistor of claim 9 , wherein the silicon channel region further comprises an n-type dopant.

13. The transistor of claim 9 , wherein the n-type dopant comprises one or both of phosphorous and arsenic.

14. The transistor of claim 9 , wherein the silicon layer comprises the n-type dopant.

15. The transistor of claim 14 , wherein the silicon layer and channel region have the substantially the same n-type dopant concentration.

16. The transistor of claim 9 , wherein the boron dopant concentration in the first portion disposed below the spacers is less than the boron dopant in the second portion.

Assignees

• Murthy Anand
• Chau Robert S
• Ghani Tahir
• Mistry Kaizad R
• Intel Corp

Inventors

• Murthy Anand
• Chau Robert S
• Ghani Tahir
• Mistry Kaizad R

Classifications

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title