Transistor, liquid crystal display device, and manufacturing method thereof

US9490350B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9490350-B2
Application numberUS-201414338380-A
CountryUS
Kind codeB2
Filing dateJul 23, 2014
Priority dateSep 10, 2010
Publication dateNov 8, 2016
Grant dateNov 8, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Photolithography and etching steps for forming an island-shaped semiconductor layer are omitted, and a liquid crystal display device is manufactured with four photolithography steps: a step of forming a gate electrode (including a wiring formed using the same layer as the gate electrode), a step of forming source and drain electrodes (including a wiring formed using the same layer as the source and drain electrodes), a step of forming a contact hole (including the removal of an insulating layer and the like in a region other than the contact hole), and a step of forming a pixel electrode (including a wiring formed using the same layer as the pixel electrode). By the reduction in the number of photolithography steps, a liquid crystal display device can be provided at low cost and high productivity. Formation of a parasitic channel is prevented by an improvement in shape and potential of a wiring.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a liquid crystal display device, comprising the steps of: forming a gate electrode and a wiring over a substrate by a first photolithography step; forming a gate insulating layer over the gate electrode; forming a semiconductor layer over the gate insulating layer; forming a source electrode and a drain electrode over the semiconductor layer by a second photolithography step; forming an insulating layer over the source electrode and the drain electrode; forming a contact hole by selectively removing a first part of the insulating layer overlapping with the drain electrode and removing a second part of the insulating layer, part of the semiconductor layer, and part of the gate insulating layer, by a third photolithography step; and forming a pixel electrode over the insulating layer by a fourth photolithography step, wherein the second part of the insulating layer, the part of the semiconductor layer, and the part of the gate insulating layer each overlap with the wiring. 2. The method for manufacturing a liquid crystal display device, according to claim 1 , wherein a base layer is formed between the substrate and the gate electrode. 3. The method for manufacturing a liquid crystal display device, according to claim 1 , wherein the semiconductor layer comprises an oxide semiconductor. 4. The method for manufacturing a liquid crystal display device, according to claim 3 , wherein the oxide semiconductor comprises indium and zinc. 5. The method for manufacturing a liquid crystal display device, according to claim 3 , wherein the insulating layer comprises at least one of materials which are included into the oxide semiconductor. 6. The method for manufacturing a liquid crystal display device, according to claim 1 , wherein the gate electrode, the source electrode, or the drain electrode is formed using a material containing copper. 7. The method for manufacturing a liquid crystal display device, according to claim 6 , wherein a highest temperature in a process after the gate electrode, the source electrode, or the drain electrode is formed is lower than or equal to 450° C. 8. The method for manufacturing a liquid crystal display device, according to claim 1 , wherein the gate electrode, the source electrode, or the drain electrode is formed using a material containing aluminum. 9. The method for manufacturing a liquid crystal display device, according to claim 8 , wherein a highest temperature in a process after the gate electrode, the source electrode, or the drain electrode is formed is lower than or equal to 380° C. 10. The method for manufacturing a liquid crystal display device, according to claim 1 , wherein the first photolithography step, the second photolithography step, the third photolithography step, and the fourth photolithography step each comprise a step of forming a resist mask, a step of etching a conductive layer or an insulating layer, and a step of removing the resist mask. 11. A method for manufacturing a liquid crystal display device, comprising the steps of: forming a gate electrode, a first wiring and a capacitor wiring over a substrate by a first photolithography step; forming a gate insulating layer over the gate electrode; forming a semiconductor layer over the gate insulating layer; forming a source electrode, a drain electrode and a second wiring over the semiconductor layer by a second photolithography step; and forming a pixel electrode over the source electrode, the drain electrode and the second wiring by a third photolithography step, wherein the first wiring is electrically connected to the gate electrode, wherein the second wiring is electrically connected to the source electrode, wherein the pixel electrode is electrically connected to the drain electrode, wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and wherein the semiconductor layer overlaps with an entirety of the pixel electrode. 12. The method for manufacturing a liquid crystal display device, according to claim 11 , wherein the capacitor wiring comprises an extending portion along the second wiring, and wherein the extending portion extends beyond the end portion of the pixel electrode in a direction parallel to a direction in which the second wiring extends. 13. The method for manufacturing a liquid crystal display device, according to claim 12 , wherein a part of the capacitor wiring or the extending portion overlaps with the pixel electrode. 14. The method for manufacturing a liquid crystal display device, according to claim 12 , wherein the extending portion comprises a bent portion or a curved portion. 15. The method for manufacturing a liquid crystal display device, according to claim 11 , wherein at least part of the first wiring is provided with a region extending beyond both end portions of the first wiring in a line width direction and covering the first wiring, and wherein the semiconductor layer does not exist in the region. 16. The method for manufacturing a liquid crystal display device, according to claim 11 , wherein the semiconductor layer comprises an oxide semiconductor. 17. The method for manufacturing a liquid crystal display device, according to claim 16 , wherein the oxide semiconductor comprises indium and zinc. 18. The method for manufacturing a liquid crystal display device, according to claim 11 , wherein the pixel electrode is electrically connected to the drain electrode with an interlayer insulator interposed therebetween. 19. The method for manufacturing a liquid crystal display device, according to claim 11 , wherein the pixel electrode is electrically connected to the drain electrode with an interlayer insulator interposed therebetween.

Assignees

Inventors

Classifications

  • Storage capacitors associated with the pixel electrode · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

  • pixel · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

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What does patent US9490350B2 cover?
Photolithography and etching steps for forming an island-shaped semiconductor layer are omitted, and a liquid crystal display device is manufactured with four photolithography steps: a step of forming a gate electrode (including a wiring formed using the same layer as the gate electrode), a step of forming source and drain electrodes (including a wiring formed using the same layer as the source…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification G02F1/136231. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).