Controlling GaAsP/SiGe interfaces

Patent metadata

Field	Value
Publication number	US-9490330-B2
Application number	US-201314432921-A
Country	US
Kind code	B2
Filing date	Oct 4, 2013
Priority date	Oct 5, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Initiation conditions and strain techniques are described that enable forming high quality GaAsP semiconductor material on an SiGe semiconductor material with low threading defect density. Suitable initiation conditions include exposing the SiGe semiconductor material to a gas comprising arsenic. A tensilely-strained region may be formed in the semiconductor structure between regions of GaAsP semiconductor material and SiGe semiconductor material.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first semiconductor region comprising a GaAsP semiconductor material;
a second semiconductor region comprising a SiGe semiconductor material; and
at least one strained semiconductor region between the first semiconductor region and the second semiconductor region, the at least one strained semiconductor region comprising a GaAsP semiconductor material and/or a SiGe semiconductor material, the at least one strained semiconductor region comprising a tensilely-strained semiconductor region,
wherein the tensilely-strained semiconductor region has a strain of no greater than approximately 0.2%.

2. The semiconductor structure of claim 1 , wherein the first semiconductor region has a lattice constant matched to that of the second semiconductor region.

3. The semiconductor structure of claim 2 , wherein the second semiconductor region is unstrained.

4. The semiconductor structure of claim 1 , wherein the tensilely-strained semiconductor region has a thickness that is less than a critical thickness for defect formation.

5. The semiconductor structure of claim 1 , wherein the tensilely-strained semiconductor region comprises a GaAsP semiconductor material.

6. The semiconductor structure of claim 1 , wherein the tensilely-strained semiconductor region comprises a SiGe semiconductor material.

7. The semiconductor structure of claim 1 , wherein the at least one strained semiconductor region comprises a GaAsP semiconductor material and a SiGe semiconductor material.

8. The semiconductor structure of claim 1 , wherein the at least one strained semiconductor region is at an interface between the first semiconductor region and the second semiconductor region.

9. The semiconductor structure of claim 1 , wherein the at least one strained semiconductor region further comprises a compressively-strained semiconductor region.

10. The semiconductor structure of claim 9 , wherein the tensilely-strained semiconductor region comprises a GaAsP semiconductor material and the compressively-strained semiconductor region comprises a GaAsP semiconductor material.

11. The semiconductor structure of claim 10 , further comprising a region of GaAsP semiconductor material lattice-matched to the second semiconductor region and being between the at least one strained semiconductor region and the second semiconductor region.

12. The semiconductor structure of claim 9 , wherein the tensilely-strained semiconductor region comprises a SiGe semiconductor material and the compressively-strained semiconductor region comprises a GaAsP semiconductor material, the tensilely-strained semiconductor region being between the compressively-strained semiconductor region and the second semiconductor region.

13. The semiconductor structure of claim 1 , wherein the first semiconductor region has a threading dislocation density of no greater than 10 6 cm −2 .

14. A semiconductor structure, comprising:
a first semiconductor region comprising a GaAsP semiconductor material;
a second semiconductor region comprising a SiGe semiconductor material; and
at least one strained semiconductor region between the first semiconductor region and the second semiconductor region, the at least one strained semiconductor region comprising a GaAsP semiconductor material and/or a SiGe semiconductor material, the at least one strained semiconductor region comprising a tensilely-strained semiconductor region,
wherein the at least one strained semiconductor region further comprises a compressively-strained semiconductor region, and
wherein the tensilely-strained semiconductor region comprises a SiGe semiconductor material and the compressively-strained semiconductor region comprises a GaAsP semiconductor material, the tensilely-strained semiconductor region being between the compressively-strained semiconductor region and the second semiconductor region.

15. The semiconductor structure of claim 14 , wherein the first semiconductor region has a lattice constant matched to that of the second semiconductor region.

16. The semiconductor structure of claim 14 , wherein the second semiconductor region is unstrained.

17. The semiconductor structure of claim 14 , wherein the tensilely-strained semiconductor region has a thickness that is less than a critical thickness for defect formation.

18. The semiconductor structure of claim 14 , wherein the first semiconductor region has a threading dislocation density of no greater than 10 6 cm −2 .

Assignees

• Massachusetts Inst Technology

Inventors

• Fitzgerald Eugene A
• Sharma Prithu
• Milakovich Timothy

Classifications

• H10P32/174

  being Group III-V material · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title