Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Method to enable controlled side chip interconnection for 3D integrated packaging system
US9136251B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136251-B2 |
| Application number | US-201213997041-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 25, 2012 |
| Priority date | Jun 25, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.
First claim
Opening claim text (preview).
What is claimed is: 1. A multi-die semiconductor structure, comprising: a first main stacked dies (MSD) structure comprising a first substantially horizontal arrangement of semiconductor dies; a second MSD structure comprising a second substantially horizontal arrangement of semiconductor dies; and an intermediate vertical side chip (i-VSC) disposed between and electrically coupled to the first and second MSD structures. 2. The multi-die semiconductor str…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9136251B2 cover?
- Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arr…
- Who is the assignee on this patent?
- Cheah Bok Eng, Periaman Shanggar, Ooi Kooi Chi, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).