Method of forming vias in silicon carbide and resulting devices and circuits

Patent metadata

Field	Value
Publication number	US-9490169-B2
Application number	US-91782810-A
Country	US
Kind code	B2
Filing date	Nov 2, 2010
Priority date	Apr 11, 2000
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a silicon carbide substrate having a first surface and a polished second surface that is opposite the first surface, wherein the polished second surface renders the silicon carbide substrate substantially transparent;
a semiconductor layer on said first surface of said silicon carbide substrate, wherein the semiconductor device defines at least one via through said silicon carbide substrate and said semiconductor layer; and
at least one contact on the semiconductor layer opposite the silicon carbide substrate, wherein the at least one contact is coated with a noble metal.

2. A semiconductor device according to claim 1 , further comprising a conductive coating within the at least one via.

3. A semiconductor device according to claim 1 , further comprising a conductive filling within the at least one via.

4. A semiconductor device according to claim 1 , wherein the at least one via extends through the entirety of the silicon carbide substrate and the semiconductor layer.

5. A semiconductor device according to claim 1 , wherein the at least one via extends from the silicon carbide substrate through the semiconductor layer to said at least one contact.

6. A semiconductor device according to claim 1 , further comprising a plurality of conductive contacts on said semiconductor layer, wherein the semiconductor device defines respective vias extending entirely through the silicon carbide substrate and said semiconductor layer such that each via terminates at a corresponding one of the plurality of conductive contacts.

7. A semiconductor device according to claim 1 , wherein said semiconductor layer is a Group III-V semiconductor epilayer.

8. A semiconductor device according to claim 1 , further comprising a polymer coating covering the entire semiconductor layer.

9. A semiconductor device according to claim 1 further comprising a transparent layer selected from a group consisting of indium-tin-oxide and magnesium oxide on the second surface of said silicon carbide substrate opposite said semiconductor layer.

10. A semiconductor device according to claim 9 , further comprising a layer of photoresist on said transparent layer.

11. A semiconductor device according to claim 1 , wherein the semiconductor layer is a Group III-V semiconductor layer.

12. A semiconductor device according to claim 1 , wherein the semiconductor layer is a Group III-V nitride layer.

Assignees

• Ring Zoltan
• Sheppard Scott Thomas
• Hagleitner Helmut
• Cree Inc

Inventors

• Ring Zoltan
• Sheppard Scott Thomas
• Hagleitner Helmut

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503 Primary

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title