Non-melt thin-wafer laser thermal annealing methods

Patent metadata

Field	Value
Publication number	US-9490128-B2
Application number	US-201213595873-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Aug 27, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Methods of annealing a thin semiconductor wafer are disclosed. The methods allow for high-temperature annealing of one side of a thin semiconductor wafer without damaging or overheating heat-sensitive electronic device features that are either on the other side of the wafer or embedded within the wafer. The annealing is performed at a temperature below the melting point of the wafer so that no significant dopant redistribution occurs during the annealing process. The methods can be applied to activating dopants or to forming ohmic contacts.

First claim

What is claimed is:

1. A method of annealing a semiconductor product wafer formed by interfacing a device wafer and a carrier wafer, wherein the device wafer has a thickness d between a front side having electronic device features and a back side having an annealing region, wherein the electronic device features are subject to being damaged beyond a critical temperature T C , the method comprising:
scanning a single continuous-wave (CW) annealing laser beam over the back side of the device wafer to anneal the annealing region by bringing the annealing region up to an anneal temperature T A that is less than a melt temperature T M of the semiconductor product wafer; and
wherein the scanning of the single CW annealing laser beam has a thermal diffusion length L D attendant therewith, and further including performing said scanning by selecting a dwell time t d that is less than a maximum dwell time t dm defined by t dm =d 2 /D eff , where D eff is an effective thermal diffusivity of the device wafer at the anneal temperature T A so that the thermal diffusion length L D satisfies L D <d and the electronic device features are maintained below the critical temperature T C , wherein 600° C. T C ≦900° C.

2. The method according to claim 1 , wherein the annealing region includes either an ion-implant layer or a contact layer.

3. The method according to claim 1 , wherein the single annealing laser beam has a visible wavelength or an infrared wavelength with an optical absorption length less than the thickness of the device wafer.

4. The method according to claim 1 , wherein the electronic device features include a CMOS device layer.

5. The method according to claim 1 , wherein the electronic device features include a semiconductor power-device layer.

6. The method according to claim 1 , wherein said scanning includes performing multiple scans of the single annealing laser beam over a same portion of the back side, wherein temporally adjacent scans are separated in time by a time interval τ, and wherein 1 millisecond≦τ≦10 seconds.

7. The method according to claim 6 , wherein the number of multiple scans is 10 or fewer.

8. The method according to claim 1 , wherein 10 μm≦d≦20 μm, and the electrical device features are made of aluminum.

9. The method according to claim 1 , wherein 10 μm≦d≦20 μm, the electrical device features are made of copper, and wherein the dwell time t d is between 15 microseconds to 100 microseconds.

10. The method according to claim 1 , wherein the electronic device features include a silicide.

11. The method according to claim 1 , wherein the annealing laser beam forms a line image at the backside of the device wafer.

Assignees

• Wang Yun
• Hawryluk Andrew M
• Wang Xiaoru
• Shen Xiaohua
• Ultratech Inc

Inventors

• Wang Yun
• Hawryluk Andrew M
• Wang Xiaoru
• Shen Xiaohua

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10P34/42 Primary

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H01L27/14634

  Electricity · mapped topic

• H01L21/02107

  Electricity · mapped topic