Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

Patent metadata

Field	Value
Publication number	US-9490012-B2
Application number	US-201514738349-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Aug 22, 2008
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

First claim

That which is claimed is:

1. A semiconductor memory cell comprising:
a bipolar device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
a buried layer terminal electrically connected to said buried layer region.

2. The semiconductor memory cell of claim 1 , wherein said resistance change element comprises a phase change material.

3. The semiconductor memory cell of claim 1 , wherein said resistance change element comprises a metal-oxide-metal system.

4. The semiconductor memory cell of claim 1 , wherein said bipolar device comprises a floating body region configured to store the state of said bipolar device.

5. The semiconductor memory cell of claim 1 , wherein one of said conditions comprises an instruction to back up said data stored in said bipolar device.

6. The semiconductor memory cell of claim 1 , wherein said nonvolatile memory stores said data stored in said bipolar device upon loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said bipolar device is loaded into and stored in said nonvolatile memory.

7. The semiconductor memory cell of claim 1 , wherein said bipolar device is fabricated on a silicon on insulator substrate.

8. The semiconductor memory cell of claim 1 , arranged in a semiconductor memory array comprising a plurality of said semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows.

9. The semiconductor memory cell of claim 1 , wherein said bipolar device is formed in a fin.

10. The semiconductor cell of claim 1 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.

11. A semiconductor memory cell comprising:
a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data as charge therein when power is applied to said cell and first and second regions located such that at least a portion of the floating body is located between said first and second regions, said capacitorless transistor configured to function as a bipolar device;
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type; and
a buried layer terminal electrically connected to said buried layer region.

12. The semiconductor memory cell of claim 11 , wherein said resistance change element comprises a bottom electrode, a resistance change material and a top electrode.

13. The semiconductor memory cell of claim 11 , wherein said resistance change element is electrically connected to said one of said first and second regions through a conductive element.

14. The semiconductor memory cell of claim 11 , wherein said resistance change element is connected to an address line.

15. The semiconductor memory cell of claim 12 , wherein said resistance change element is connected to an address line through said top electrode.

16. The semiconductor memory cell of claim 11 , wherein said resistance change element comprises a phase change material.

17. The semiconductor memory cell of claim 11 , wherein said resistance change element comprises a metal-oxide-metal system.

18. A semiconductor memory cell comprising:
a bipolar device configured to store data when power is applied to said cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said bipolar device upon transfer thereto under any one of a plurality of predetermined conditions;
wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said bipolar device is loaded into and stored in said nonvolatile memory;
wherein, upon restoration of power to said cell, said data in said nonvolatile is loaded into said bipolar device and stored therein; and
wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

19. The semiconductor memory cell of claim 18 , wherein said transfer occurs in response to an instruction to back up said data stored in said bipolar device.

Assignees

• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto

Classifications

• G06F3/0647

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• G11C13/0033

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• G11C2211/5643

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