Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

Patent metadata

Field	Value
Publication number	US-9087580-B2
Application number	US-201113244812-A
Country	US
Kind code	B2
Filing date	Sep 26, 2011
Priority date	Aug 22, 2008
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

First claim

That which is claimed is:

1. A semiconductor memory cell comprising:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and
a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;
wherein said capacitorless transistor and said non-volatile memory are connected in series;
wherein current flowing to said resistance change element flows through said floating body;
wherein one of said predetermined conditions comprises loss of power to said cell;
wherein said cell is configured to perform a shadowing process when said data in said floating body is loaded into and stored in said nonvolatile memory;
wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and
wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

2. The semiconductor memory cell of claim 1 , wherein said resistance change element comprises a phase change material.

3. The semiconductor memory cell of claim 1 , wherein said resistance change element comprises a metal-oxide-metal system.

4. The semiconductor memory cell of claim 1 wherein one of said conditions comprises an instruction to back up said data stored in said floating body.

5. The semiconductor memory cell of claim 1 , wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein intentional power loss is predetermined to conserve power.

6. The semiconductor memory cell of claim 1 , wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said high resistance state.

7. The semiconductor memory cell of claim 1 , wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said low resistance state.

8. The semiconductor memory cell of claim 1 , arranged in a semiconductor memory array comprising a plurality of said semiconductor memory cells arranged in a matrix of at least one row and a plurality of columns or at least one column and a plurality of rows.

9. A semiconductor memory cell comprising:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and
a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body under any one of a plurality of predetermined conditions;
wherein said capacitorless transistor and said non-volatile memory are connected in series;
wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;
wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and
wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

10. The semiconductor memory cell of claim 9 , wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said high resistance state.

11. The semiconductor memory cell of claim 9 , wherein said resistance change element is configured to be set to a high resistance state in a first state and is configured to be set to a low resistance state as a second state, and wherein said reset to said initial state comprises resetting said resistance change element to said low resistance state.

12. A semiconductor memory cell comprising:
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said cell; and
a non-volatile memory comprising a resistance change element configured to receive transfer of data stored in said floating body upon unintentional power loss or intentional power loss to said cell;
wherein said capacitorless transistor and said non-volatile memory are connected in series;
wherein said cell is configured to perform a shadowing process wherein said data in said floating body is loaded into and stored in said nonvolatile memory;
wherein, upon restoration of power to said cell, said data in said nonvolatile memory is loaded into said floating body and stored therein; and
wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said floating body upon said restoration of power.

Assignees

• Widjaja Yuniarto
• Zeno Semiconductor Inc

Inventors

• Widjaja Yuniarto

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C11/4067

  for memory cells of the bipolar type · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C2213/31

  Material having complex metal oxide, e.g. perovskite structure · CPC title