Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric

Patent metadata

Field	Value
Publication number	US-9484460-B2
Application number	US-201314032153-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Sep 19, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first type region comprising a first conductivity type;
a second type region comprising a second conductivity type;
a channel region extending between the first type region and the second type region;
a drift region extending between the channel region and the second type region;
a gate dielectric surrounding at least some of the channel region;
a gate electrode surrounding at least some of the gate dielectric, wherein the gate electrode and the drift region are not laterally co-planar; and
a dielectric extending between the gate dielectric and the first type region.

2. The semiconductor device of claim 1 , wherein the dielectric is in contact with a top surface and a sidewall of the first type region.

3. The semiconductor device of claim 1 , wherein the first type region comprises a diffusion portion in contact with the channel region and the dielectric is in contact with a sidewall of the diffusion portion.

4. The semiconductor device of claim 1 , wherein a gate length of the gate electrode is between about 5 nm to about 25 nm.

5. The semiconductor device of claim 1 , wherein the first type region comprises a source region.

6. The semiconductor device of claim 5 , wherein the second type region comprises a drain region.

7. The semiconductor device of claim 1 , wherein the first conductivity type of the first type region comprises an n-type material.

8. The semiconductor device of claim 7 , wherein the second conductivity type of the second type region comprises an n-type material.

9. The semiconductor device of claim 1 , wherein the first conductivity type of the first type region comprises a p-type material.

10. The semiconductor device of claim 9 , wherein the second conductivity type of the second type region comprises a p-type material.

11. A semiconductor device, comprising:
a first type region comprising a first conductivity type;
a second type region comprising a second conductivity type;
a channel region extending between the first type region and the second type region;
a drift region extending between the channel region and the second type region;
a gate dielectric surrounding at least some of the channel region;
a gate electrode surrounding at least some of the gate dielectric; and
a dielectric, wherein a bottom surface of the gate dielectric is in contact with the dielectric and wherein the dielectric is in contact with the drift region.

12. The semiconductor device of claim 11 , wherein a sidewall of the first type region is in contact with the dielectric.

13. The semiconductor device of claim 11 , wherein a top surface of the first type region is in contact with the dielectric.

14. The semiconductor device of claim 11 , wherein a bottom surface of the gate electrode is in contact with the dielectric.

15. The semiconductor device of claim 11 , wherein a bottom surface, a sidewall, and a top surface of the gate electrode are in contact with the dielectric.

16. The semiconductor device of claim 11 , wherein the first type region comprises a source region.

17. The semiconductor device of claim 16 , wherein the second type region comprises a drain region.

18. A semiconductor device, comprising:
a first type region comprising a first conductivity type;
a second type region comprising a second conductivity type;
a channel region extending between the first type region and the second type region, the first type region in contact with the channel region;
a drift region extending between the second type region and the channel region;
a gate dielectric surrounding at least some of the channel region;
a gate electrode surrounding at least some of the gate dielectric; and
a dielectric in contact with the drift region, the dielectric different than the gate dielectric.

19. The semiconductor device of claim 18 , wherein a top surface of the gate dielectric is in contact with the dielectric.

20. The semiconductor device of claim 18 , wherein a top surface of the gate electrode is in contact with the dielectric.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean-Pierre
• Yu Tsung-Hsing
• Hsu Yeh
• Liu Chia-Wen
• Diaz Carlos H

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title

• H10D30/64

  Double-diffused metal-oxide semiconductor [DMOS] FETs · CPC title

• H10D30/0221

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS] · CPC title