Package-on-package structure with reduced height

Patent metadata

Field	Value
Publication number	US-9484327-B2
Application number	US-201313833921-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

First claim

What is claimed is:

1. A device, comprising:
a first package substrate having a window extending entirely through the first package substrate;
a first package die;
a plurality of first interconnects in direct contact with both the first package substrate and the first package die, wherein the plurality of first interconnects is configured to provide a first electrical connection for a first signal between the first package die and the first package substrate;
a second package substrate interconnected to the first package substrate through a plurality of package-to-package interconnects, the first package substrate comprising a first surface facing the second package substrate and a second surface facing away from the second package substrate;
a second package die;
a plurality of second interconnects in direct contact with both the second package substrate and the second package die, wherein the plurality of second interconnects is configured to provide a direct second electrical connection for a second signal between the second package die and the second package substrate, and wherein the second package die is disposed at least partially within the window; and
a mold compound configured to encapsulate the second package die and to have a surface aligned in a plane with the second surface of the first package substrate, wherein the mold compound is further configured to encapsulate the package-to-package interconnects.

2. The device of claim 1 , wherein the plurality of second interconnects are flip-chip interconnects.

3. The device of claim 1 , wherein the first package die is attached to a mold compound surface.

4. The device of claim 3 , wherein the plurality of first interconnects comprise a plurality of wire bond interconnects.

5. The device of claim 3 , wherein the circuit is incorporated into at least one of a cellphone, a laptop, a tablet, a music player, a communication device, a computer, and a video player.

6. The device of claim 3 , wherein the first package die comprises a plurality of first package dies.

7. The device of claim 1 , wherein the second package die is mounted over the second package substrate and, wherein the second package die is substantially co-planar with the first package substrate.

8. The device of claim 1 , wherein the second package die comprises an active surface that faces the second package substrate.

9. The device of claim 1 , wherein the first package die comprises a first non-active surface, and the second package die comprises a second non-active surface, and wherein the first non-active surface of the first package die faces the second non-active surface of the second package die.

10. The device of claim 1 , wherein the second package die is configured to be directly interconnected to the second package substrate through the plurality of second interconnects such that the first package substrate can be bypassed.

Assignees

• Qualcomm Inc

Inventors

• Kim Chin-Kwan
• Bchir Omar James
• Shah Milind Pravin
• Hsu Marcus Bernard
• Rae David Fraser

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title