Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
US-2024404859-A1 · Dec 5, 2024 · US
US9484243B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9484243-B2 |
| Application number | US-201414255730-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 17, 2014 |
| Priority date | Apr 17, 2014 |
| Publication date | Nov 1, 2016 |
| Grant date | Nov 1, 2016 |
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A processing chamber having a chamber housing with a top and sidewalls is provided. The processing chamber has a seal for connecting the sidewalls of the chamber housing to a top of a lower chamber below the processing chamber. A substrate holder is attached to the sidewalls of the chamber housing. Further, a wafer lift ring supported by a side arm extending through the sidewalls has at least three posts each having at least one finger, the top of the fingers defining a first wafer handoff plane. The lower chamber has at least one lowest wafer support that defines a second wafer handoff plane where the height between the first wafer handoff plane and the second wafer handoff plane is not greater than a maximum vertical stroke of a transfer arm that is configured to transfer a wafer from the first wafer handoff plane and the second wafer handoff plane.
Opening claim text (preview).
What is claimed is: 1. A processing chamber, comprising: a chamber housing having a top and sidewalls; a seal for connecting the sidewalls of the chamber housing to a top of a lower chamber positioned below the processing chamber; a substrate holder that is attached to the sidewalls of the chamber housing; a wafer lift ring supported by a side arm extending through the sidewalls of the chamber housing, wherein the wafer lift ring has at least three posts that stand verticall…
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