Gate contact for a semiconductor device and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9343543-B2
Application number	US-201514603906-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Mar 13, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a semiconductor structure and a dielectric layer on a surface of the semiconductor structure, where the dielectric layer has an opening that exposes an area of the semiconductor structure. A gate contact for the semiconductor device is formed on the exposed area of the semiconductor structure through the opening in the dielectric layer. The gate contact includes a proximal end on a portion of the exposed area of the semiconductor structure, a distal end opposite the proximal end, and sidewalls that each extend between the proximal end and the distal end of the gate contact. For each sidewall of the gate contact, an air region separates the sidewall and the distal end of the gate contact from the dielectric layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device comprising:
providing a semiconductor structure;
providing a first dielectric layer on the semiconductor structure;
providing a second dielectric layer on the first dielectric layer opposite the semiconductor structure;
forming a first opening in the first and second dielectric layers to expose an area of the semiconductor structure and thereby provide an exposed area of the semiconductor structure;
forming spacers adjacent to sidewalls of the first opening in the first and second dielectric layers, the spacers defining a second opening between the spacers that has a length that is substantially less than a length of the first opening;
providing a gate contact within the second opening such that a proximal end of the gate contact is on a portion of the exposed area of the semiconductor structure that is exposed by the second opening; and
removing the spacers and the second dielectric layer such that, for each sidewall of the gate contact, an air region separates the sidewall of the gate contact from the first dielectric layer.

2. The method of claim 1 wherein, for each sidewall of the gate contact, the air region further separates the distal end of the gate contact from the first dielectric layer.

3. The method of claim 1 wherein forming the spacers comprises:
providing a spacer material layer on the second dielectric layer opposite the first dielectric layer and on the exposed area of the semiconductor structure within the first opening in the first and second dielectric layers; and
anisotropically etching the spacer material layer in a direction that is perpendicular to the semiconductor structure such that the spacers are formed adjacent to the sidewalls of the first opening in the first and second dielectric layers.

4. The method of claim 1 wherein the proximal end of the gate contact is directly on the portion of the exposed area of the semiconductor structure that is exposed by the second opening.

5. The method of claim 4 wherein a length of the second opening and thus a length of the proximal end of the gate contact is less than a length of the distal end of the gate contact.

6. The method of claim 4 wherein a length of the second opening and thus a gate length of the semiconductor device is less than or equal to 0.15 micrometers.

7. The method of claim 4 wherein a length of the second opening and thus a gate length of the semiconductor device is in a range of and including 0.05 to 0.25 micrometers.

8. The method of claim 4 wherein a length of the second opening and thus a gate length of the semiconductor device is in a range of and including 0.05 to 0.15 micrometers.

9. The method of claim 4 wherein a length of the second opening and thus a gate length of the semiconductor device is in a range of and including 0.05 to 0.1 micrometers.

10. The method of claim 4 further comprising providing a field plate on a surface of the first dielectric layer adjacent to the gate contact.

11. The method of claim 10 wherein providing the field plate comprises:
providing a photoresist layer on the first dielectric layer and the gate contact;
forming an opening in the photoresist layer over a portion of the gate contact and an adjacent portion of the first dielectric layer;
forming a field plate metal on the photoresist layer and within the opening in the photoresist layer; and
removing the photoresist layer and a portion of the field plate metal that is on the photoresist layer such that a remaining portion of the field plate metal on the surface of the first dielectric layer adjacent to the gate contact forms the field plate where a first edge of the field plate is aligned with an edge of the distal end of the gate contact and extends laterally away from the gate contact to a second edge of the field plate.

12. The method of claim 11 wherein the air region that separates the sidewall of the gate contact that is adjacent to the field plate and the distal end of the gate contact from the first dielectric layer further separates the field plate from an adjacent one of the sidewalls of the gate contact, the distal end of the gate contact, and a residual field plate metal on the distal end of the gate contact.

13. The method of claim 1 further comprising:
after forming the first opening in the first and second dielectric layers, etching the semiconductor structure through the first opening to form an outer recess that is aligned with the first opening in the first and second dielectric layers and extends from a surface of the semiconductor structure to a first depth in the semiconductor structure; and
after forming the spacers, etching the semiconductor structure through the second opening provided by the spacers to form an inner recess that is within the outer recess and extends from a bottom of the outer recess to a second depth in the semiconductor structure;
wherein providing the gate contact comprises forming the gate contact within the second opening provided by the spacers such that the proximal end of the gate contact is aligned with and is within the inner recess in the semiconductor structure and is directly on a portion of the semiconductor structure within the inner recess.

14. The method of claim 13 wherein, for each sidewall of the sidewalls of the gate contact, the air region that separates the sidewall and the distal end of the gate contact from the first dielectric layer also separates the sidewall of the gate contact from a sidewall of the outer recess.

15. The method of claim 1 further comprising:
after forming the first opening in the first and second dielectric layers, etching the semiconductor structure through the first opening to form a recess that is aligned with the first opening in the first and second dielectric layers and extends from a surface of the semiconductor structure to a desired depth in the semiconductor structure;
wherein providing the gate contact comprises forming the gate contact within the second opening provided by the spacers such that the proximal end of the gate contact is directly on a portion of the semiconductor structure exposed by the second opening.

16. The method of claim 15 wherein, for each sidewall of the sidewalls of the gate contact, the air region that separates the sidewall and the distal end of the gate contact from the first dielectric layer also separates the sidewall of the gate contact from a sidewall of the recess.

17. The method of claim 1 further comprising:
after forming the spacers, etching the semiconductor structure through the second opening provided by the spacers to form a recess that is aligned with the second opening and extends from a surface of the semiconductor structure to a desired depth in the semiconductor structure;
wherein providing the gate contact comprises forming the gate contact within the second opening provided by the spacers such that the proximal end of the gate contact is aligned with and is within the recess in the semiconductor structure and is directly on a portion of the semiconductor structure within the recess.

Assignees

• Cree Inc

Inventors

• Radulescu Fabian
• Hagleitner Helmut

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D64/0121

  to Group IV semiconductors · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title