Phase shifter for linearly shifting phase of input signal based on phase control signals

Patent metadata

Field	Value
Publication number	US-12224728-B2
Application number	US-202318182571-A
Country	US
Kind code	B2
Filing date	Mar 13, 2023
Priority date	Apr 1, 2022
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

First claim

What is claimed is:

1. A phase shift circuit, comprising:
a signal generator configured to generate an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal based on an input signal;
a controller configured to generate a first selection signal, a second selection signal, a first control signal, and a second control signal;
a vector adder; and
a digital-to-analog converter configured to generate a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal based on the first control signal and the second control signal,
wherein the vector adder includes:
an input circuit;
a switching circuit configured to shift each of phases of a first internal signal, a second internal signal, a third internal signal, and a fourth internal signal received from the input circuit and output a first shift signal, a second shift signal, a third shift signal, and a fourth shift signal; and
an output circuit configured to generate an output signal based on the first to fourth shift signals,
wherein the input circuit includes:
a first transistor connected between a ground node for receiving ground power and a first node for generating the first internal signal and configured to operate based on the in-phase signal and the first bias signal;
a second transistor connected between the ground node and a second node for generating the second internal signal and configured to operate based on the complementary in-phase signal and the first bias signal;
a third transistor connected between the ground node and the first node and configured to operate based on the second bias signal;
a fourth transistor connected between the ground node and the second node and configured to operate based on the second bias signal;
a fifth transistor connected between the ground node and a third node for generating the third internal signal and configured to operate based on the quadrature phase signal and the second bias signal;
a sixth transistor connected between the ground node and a fourth node for generating the fourth internal signal and configured to operate based on the complementary quadrature phase signal and the second bias signal;
a seventh transistor connected between the ground node and the third node and configured to operate based on the first bias signal; and
an eighth transistor connected between the ground node and the fourth node and configured to operate based on the first bias signal, and wherein each of the first control signal and the second control signal includes N bits, where N is a natural number of 2 or more.

2. The phase shift circuit of claim 1 , wherein the input circuit further includes:
a first resistor connected between a gate node of the first transistor and a fifth node for receiving the first bias signal;
a second resistor connected between a gate node of the second transistor and the fifth node;
a third resistor connected between a gate node of the third transistor and a sixth node for receiving the second bias signal;
a fourth resistor connected between a gate node of the fifth transistor and the sixth node;
a fifth resistor connected between a gate node of the sixth transistor and the sixth node; and
a sixth resistor connected between a gate node of the seventh transistor and the fifth node.

3. The phase shift circuit of claim 1 , wherein the input circuit further includes:
a first capacitor connected between a first input node for receiving the in-phase signal and a gate node of the first transistor;
a second capacitor connected between a second input node for receiving the complementary in-phase signal and a gate node of the second transistor;
a third capacitor connected between a third input node for receiving the quadrature phase signal and a gate node of the fifth transistor; and
a fourth capacitor connected between a fourth input node for receiving the complementary quadrature phase signal and a gate node of the sixth transistor.

4. The phase shift circuit of claim 1 , wherein the switching circuit includes:
a ninth transistor having a gate node connected with a seventh node for receiving the first selection signal and connected between an eighth node for generating the first internal signal and the first node;
a first inverter connected between the seventh node and a ninth node;
a tenth transistor having a gate node connected with the ninth node and connected between a tenth node for generating the second internal signal and the first node;
an eleventh transistor connected between a gate node connected with the ninth node and connected between the eighth node and the second node;
a twelfth transistor connected between a gate node connected with the seventh node and connected between the tenth node and the second node;
a 13th transistor having a gate node connected with an eleventh node for receiving the second selection signal and connected between a twelfth node for generating the third internal signal and the third node;
a second inverter connected between the eleventh node and a 13th node;
a 14th transistor having a gate node connected with the 13th node and connected between a 14th node for generating the fourth internal signal and the third node;
a 15th transistor having a gate node connected with the 13th node and connected between the twelfth node and the fourth node; and
a 16th transistor having a gate node connected with the eleventh node and connected between the 14th node and the fourth node.

5. The phase shift circuit of claim 4 , wherein the output circuit includes:
a 17th transistor having a gate node connected with a 15th node for receiving the third bias signal and connected between a 16th node and the eighth node;
an 18th transistor having a gate node connected with the 15th node and connected between a 17th node and the tenth node;
a 19th transistor having a gate node connected with an 18th node for receiving the fourth bias signal and connected between the 16th node and the twelfth node;
a 20th transistor having a gate node connected with the 18th node and connected between the 17th node and the 14th node; and
a load connected between the 16th node and the 17th node, and
wherein the output signal has a voltage level being a difference between a voltage level of the 16th node and a voltage level of the 17th node.

6. The phase shift circuit of claim 1 , wherein the digital-to-analog converter includes:
a first current source connected between a power node for receiving a power voltage and a 19th node and configured to operate based on the first control signal;
a 21st transistor having a gate node connected with the 19th node for receiving the third bias signal and connected between the 19th node and a 20th node;
a 22nd transistor having a gate node connected with the 20th node for receiving the first bias signal and connected between the 20th node and the ground node;
a second current source connected between the power node and a 21st node and configured to operate based on the second control signal;
a 23rd transistor having a gate node connected with the 21st node for receiving the fourth bias signal and connected between the 21st node and a 22nd node; and
a 24th transistor having a gate node connected with the 22nd node for receiving the second bias signal and connected between the 22nd node and the ground node.

7. The phase shift circuit of claim 6 , wherein the first current source includes:
a PMOS transistor having a gate node connected with a 23rd node and connected between the power node and a 24th node;
a second PMOS transistor having a gate node connected with a 25th node for receiving a first bit of the first control signal and connected between the 24th node and a 26th node;
a third in

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Han Seon-Ho
• Koo Bon Tae

Classifications

• H03H11/20 Primary

  Two-port phase shifters providing an adjustable phase shift · CPC title

• H01P1/18

  Phase-shifters (H01P1/165 takes precedence) · CPC title

• H03H11/18 Primary

  Two-port phase shifters providing a predetermined phase shift, e.g. "all-pass" filters · CPC title

• H03H11/16 Primary

  Networks for phase shifting · CPC title