Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns

Patent metadata

Field	Value
Publication number	US-9478736-B2
Application number	US-201313835868-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

First claim

What is claimed is:

1. A memory array device comprising:
memory cells;
a plurality of memory cell pillars, each memory cell pillar including:
(a) a field effect transistor (FET) over a substrate, the FET including a FET channel;
(b) a memory element electrically coupled to the FET, the memory element including a plurality of memory element layers wherein the memory element layers are epitaxially grown on top of the FET; and
(c) an encapsulation layer surrounding the memory element providing ohmic contact between the memory element and a bit line, the encapsulation layer and the FET aligned to form straight sides of the memory cell pillar;

a plurality of gate conductors configured along a first axis in parallel, wherein each FET of the memory cells is adjacent to two gate conductors;
a gate oxide continuously extending along an array column of the memory array device and in contact with the straight sides of the memory cell pillar for each of the memory cells;
a dielectric row filler layer extending along sides of the memory cell pillars and in contact with the FET channel and the memory element of each memory cell pillar; and
a plurality of bit lines configured along a second axis in parallel, wherein each bit line is electrically coupled to a plurality of memory elements of the memory cells along the second axis, the second axis being perpendicular to the first axis.

2. The memory array device of claim 1 , wherein the FET includes a plurality of FET layers, the plurality of FET layers including alternating layers of n-type doped silicon and p-type silicon.

3. The memory array device of claim 1 , wherein each memory cell includes a seed layer between the memory element and the FET, the seed layer including a plurality of sub-layers configured to fulfill the following functions:
(a) provide ohmic contact between the FET and the memory element;
(b) promote magnetic anisotropy for the memory element layers; and
(c) compensate mismatch between the FET crystal lattices and memory element crystal lattices.

4. The memory array device of claim 1 , wherein a space between the plurality of gate conductors is substantially less than a space between a plurality of bit lines.

5. The memory array device of claim 1 , wherein at least one dimension of the memory elements is substantially smaller than the FETs.

6. The memory array device of claim 1 , wherein the plurality of memory element layers include a free-magnetic layer, a tunnel barrier, and a fixed-magnetic layer.

7. The memory array device of claim 1 , further comprising:
wherein each of the memory cell pillar includes a first N+ doped region, a second N+ doped region, and a P doped region positioned between the first N+ doped region and the second N+ doped region, the first N+ doped region, the second N+ doped region, and P doped region located at the memory cell pillar and forming the FET; and
the gate oxide continuously extending along and in contact with each of the first N+ doped region, the second N+ doped region, and P doped region located at the memory cell pillar.

Assignees

• IBM

Inventors

• Debrosse John K
• Lam Chung H
• Nowak Janusz J

Classifications

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title