Solid-state imaging device and electronic device

US9478569B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9478569-B2
Application numberUS-201414512200-A
CountryUS
Kind codeB2
Filing dateOct 10, 2014
Priority dateOct 18, 2013
Publication dateOct 25, 2016
Grant dateOct 25, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with respect to the power supply wiring nearly uniform. As a result, it is possible to suppress variation of load capacitance of the vertical signal line for each pixel. It becomes possible to suppress deviation in a black level, variation of charge transfer, and variation of settling. It becomes possible to obtain an image with higher quality.

First claim

Opening claim text (preview).

The invention claimed is: 1. An imaging device comprising: a substrate including a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion section; a first wiring layer including a plurality of wirings coupled to the plurality of pixels, wherein the plurality of wirings of the first wiring layer extend in a first direction parallel to a light-incident surface of the substrate; and a second wiring layer including one or more power supply wirings that overlap adjacent wirings of the plurality of wirings of the first wiring layer in a second direction perpendicular to the light-incident surface of the substrate, wherein, an area of regions where the one or more power supply wirings overlap the plurality of wirings of the first wiring layer are substantially uniform, and the one or more power supply wirings extend in a third direction parallel to the light-incident surface of the substrate and overlap the plurality of wirings of the first wiring layer at an oblique angle. 2. The imaging device according to claim 1 , wherein the first wiring layer is disposed between the substrate and the second wiring layer. 3. The imaging device according to claim 1 , wherein the second wiring layer includes one or more power supply wirings that extend in a fourth direction parallel to the light-incident surface of the substrate and perpendicular to the third direction. 4. The imaging device according to claim 1 , wherein the second wiring layer is disposed on the first wiring layer. 5. The imaging device according to claim 1 , wherein at least one wiring of the plurality of wirings is a signal line provided to read out a voltage signal depending upon charge obtained by one or more photoelectric conversion sections. 6. The imaging device according to claim 1 , wherein at least one wiring of the plurality of wirings is driver wiring provided to drive elements provided in the pixel. 7. The imaging device according to claim 1 , wherein the imaging device is a back-irradiation type imaging device. 8. The imaging device according to claim 1 , wherein at least one power supply wiring of the one or more power supply wirings is wider in a direction parallel to the light-incident surface of the substrate than a width of a pixel. 9. An electronic device including an imaging device, the imaging device comprising: a substrate including a plurality of pixels, wherein each pixel of the plurality of pixels includes a photoelectric conversion section; a first wiring layer including a plurality of wirings coupled to the plurality of pixels, wherein the plurality of wirings of the first wiring layer extend in a first direction parallel to a light-incident surface of the substrate; and a second wiring layer including one or more power supply wirings that overlap the plurality of wirings of the first wiring layer in a second direction perpendicular to the light-incident surface of the substrate, wherein, an area of regions where the one or more power supply wirings overlap the plurality of wirings of the first wiring layer are substantially uniform, and the one or more power supply wirings extend in a third direction parallel to the light-incident surface of the substrate and overlap the plurality of wirings of the first wiring layer at an oblique angle. 10. The electronic device according to claim 9 , wherein the first wiring layer is disposed between the substrate and the second wiring layer. 11. The electronic device according to claim 9 , wherein the second wiring layer includes one or more power supply wirings that extend in a fourth direction parallel to the light-incident surface of the substrate and perpendicular to the third direction. 12. The electronic device according to claim 9 , wherein the second wiring layer is disposed on the first wiring layer. 13. The electronic device according to claim 9 , wherein at least one wiring of the plurality of wirings is a signal line provided to read out a voltage signal depending upon charge obtained by one or more photoelectric conversion sections. 14. The electronic device according to claim 9 , wherein at least one wiring of the plurality of wirings is driver wiring provided to drive elements provided in the pixel. 15. The electronic device according to claim 9 , wherein the imaging device is a back-irradiation type imaging device. 16. The electronic device according to claim 9 , wherein at least one power supply wiring of the one or more power supply wirings is wider in a direction parallel to the light-incident surface of the substrate than a width of a pixel.

Assignees

Inventors

Classifications

  • Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

  • H10F39/802Primary

    Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9478569B2 cover?
The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided right under power supply wiring apart from a floating diffusion region in order to reduce load capacitance of the vertical signal line. Furthermore, the power supply wiring is wired to make a cover rate of each vertical signal line with re…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/802. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 25 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).