Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration

Patent metadata

Field	Value
Publication number	US-9478533-B2
Application number	US-201514714369-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Jan 31, 2013
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

First claim

What is claimed is:

1. A method of manufacturing integrated circuits, the method comprising:
forming a plurality of gate electrode lines separated by a gate electrode pitch to form a standard cell device;
applying at least a first layer of metal between adjacent gate electrode lines to form a portion of a resistor; and
applying at least a second layer of metal to directly couple to the first layer of metal to form another portion of the resistor.

2. The method of claim 1 , the method further comprising applying metal to connect a circuit from a first power domain to an input of the resistor.

3. The method of claim 2 , wherein the standard cell device comprises a gate grounded NMOS device.

4. The method of claim 3 , the method further comprising applying metal to connect an output of the resistor to the gate grounded NMOS device.

5. The method of claim 4 the method further comprising applying metal to connect the output of the resistor to a circuit from a second power domain.

6. The method of claim 1 , wherein the standard cell device and the resistor form a charged device model (CDM) electrostatic discharge (ESD) protection circuit in a cross power domain.

7. The method of claim 6 , the method further comprising applying at least a third layer of metal through at least first, second, and third vias in a multilayered substrate to form a connection between an input port of the CDM ESD protection circuit and an output port of the CDM ESD protection circuit.

8. The method of claim 7 , wherein the standard cell device comprises a gate grounded NMOS device and wherein the method further comprises a connection of the third layer of metal through the third via to an oxide layer to form a MOS drain of the gate grounded NMOS device.

9. The method of claim 6 , wherein the CDM ESD protection circuit is arranged and constructed without a keep out zone between adjacent cells of the standard cell device.

10. A method of manufacturing integrated circuits, the method comprising:
forming a plurality of gate electrode lines at a first layer above active regions formed in a substrate, to form a standard cell device, the gate electrode lines separated from each other by a gate electrode pitch;
at the first layer, forming a first metal contact located between one of the gate electrode lines and another of the gate electrode lines that is adjacent to said one gate electrode line on a first side of said one gate electrode line;
at the first layer, forming a second metal contact located between said one gate electrode line and another of the gate electrode lines that is adjacent to said one gate electrode line on a second side of said one gate electrode line; and
at a second layer, forming a third metal contact connecting the first and second metal contacts, the third metal contact located above said one gate electrode line.

11. The method of claim 10 , further comprising:
at the second layer, forming a fourth metal contact above said first metal contact; and
at the second layer, forming a fifth metal contact above said second metal contact.

12. The method of claim 11 , wherein the third metal contact abuts the fourth and fifth metal contacts.

13. The method of claim 11 , wherein the fourth metal contact and the fifth metal contact are made of a same material as the first metal contact and the second metal contact, respectively.

14. The method of claim 10 , wherein the first, second, and third metal contacts are portions of a resistor, the method further comprising applying metal to connect a circuit from a first power domain to an input of the resistor.

15. The method of claim 14 , wherein the standard cell device comprises a gate grounded NMOS device.

16. The method of claim 15 , further comprising applying metal to connect an output of the resistor to the gate grounded NMOS device.

17. The method of claim 16 , further comprising applying metal to connect the output of the resistor to a circuit from a second power domain.

18. The method of claim 14 , wherein the standard cell device and the resistor form a charged device model (CDM) electrostatic discharge (ESD) protection circuit in a cross power domain.

19. A method of manufacturing integrated circuits, the method comprising:
forming a plurality of gate electrode lines at a first layer above active regions formed in a substrate, the gate electrode lines separated from each other by a gate electrode pitch;
at the first layer, forming a first set of metal contacts, each metal contact in the first set being disposed between a pair of adjacent gate electrode lines in the plurality of gate electrode lines; and
at a second layer above the first layer, forming a second set of metal contacts, the second set including a first metal contact located near a first end of a first metal contact in the first set of metal contacts, the second set further including a second metal contact located near a second end of a second metal contact in the first set of metal contacts.

20. The method of claim 19 , wherein the first metal contact includes a portion formed above a first gate electrode line of the plurality of gate electrode lines and the second metal contact includes a portion formed above a second gate electrode line of the plurality of gate electrode lines, the first and second gate electrode lines neighboring one another;
wherein the second set of metal contacts further includes a third metal contact located at the first displacement along the length dimension of the first set of metal contacts, the third metal contact including a portion formed above a third gate electrode line of the plurality of gate electrode lines, the second and third gate electrode lines neighboring one another.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ma wei yu
• Chen Bo-Ting
• Chen ting yu
• Chen Kuo-Ji
• Tien Li-Chun

Classifications

• H10D1/474

  comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title