Real time analysis and control for a multiprocessor system

Patent metadata

Field	Value
Publication number	US-9477585-B2
Application number	US-201314074925-A
Country	US
Kind code	B2
Filing date	Nov 8, 2013
Priority date	Nov 9, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.

First claim

We claim:

1. A method for testing a device under test (DUT) that comprises a multiprocessor array (MPA) executing application software, the method comprising:
storing application software that is desired to be tested, wherein the application software is deployable to execute on first hardware resources of the MPA, wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network (IN) communicatively coupling the plurality of processing elements and the plurality of memories;
modifying the application software that is desired to be tested to include testing code, thereby creating modified application software, wherein the testing code in the modified application software includes at least one auxiliary send statement;
deploying the modified application software on hardware resources of the MPA, wherein said deploying comprises deploying the application software to use the first hardware resources of the MPA and deploying the test code to execute on at least one of the first hardware resources and configured to use one or more second hardware resources of the MPA, wherein the second hardware resources are different from the first hardware resources and are not used by the application software, wherein the MPA executing the modified application software in real time at full operational speed comprises the device under test (DUT);
receiving, by the modified application software, input data to stimulate the DUT;
generating, by the modified application software, first data in the DUT based on the input data;
executing, by the modified application software, a first send statement which provides the first data for use in the modified application software, wherein the first send statement executes on one of the first hardware resources of the MPA;
executing, by the modified application software, an auxiliary send statement on one of the first hardware resources to provide at least a subset of the first data to a pin at an edge of the MPA using at least one of the one or more second hardware resources of the MPA; and
receiving the at least a subset of the first data provided by the auxiliary send statement, wherein the first data are useable for analyzing operation of the DUT.

2. The method of claim 1 , wherein said executing the auxiliary send statement to provide the at least a subset of the first data to the pin at the edge of the MPA programs a first direct memory access (DMA) engine of the MPA to provide the at least a subset of the first data to the pin at the edge of the MPA, and wherein the first DMA engine is one of the second hardware resources.

3. The method of claim 2 ,
wherein said generating comprises storing the first data in a first memory of the MPA, wherein the first memory is one of the first hardware resources used by the application software, wherein a plurality of DMA engines are associated with the first memory, including the first DMA engine that is one of the one or more second hardware resources.

4. The method of claim 3 ,
wherein a second DMA engine is associated with the first memory, wherein the second DMA engine is one of the first hardware resources used by the application software.

5. The method of claim 1 , wherein said modifying the application software comprises:
analyzing the application software to locate the first send statement in the application software; and
automatically inserting the auxiliary send statement in the application software proximate to the first send statement.

6. The method of claim 1 , wherein said modifying the application software comprises:
analyzing the application software to locate a plurality of send statements in the application software; and
automatically inserting a corresponding one or more auxiliary send statements in the application software proximate to respective ones of the plurality of send statements.

7. The method of claim 1 , wherein said modifying the application software comprises:
manually inserting one or more auxiliary send statements in the application software proximate to respective ones of a plurality of send statements in the application software.

8. The method of claim 1 ,
wherein the first data are provided for use by the modified application software via a first data path through the IN of the MPA, and
wherein the at least a subset of the first data are provided to the pin at the edge of the MPA via a second data path through the IN of the MPA, wherein the second data path is different from the first data path.

9. The method of claim 1 , wherein said executing the auxiliary send statement comprises filtering the first data, thereby generating the at least a subset of the first data.

10. The method of claim 1 , wherein the DUT is configured to:
receiving, by the DUT, real time data from an external signal source coupled to the DUT to stimulate the DUT.

11. The method of claim 1 , wherein said modifying and said receiving are performed by a software defined test bench, wherein the software defined test bench tests the DUT with negligible impact on DUT performance.

12. A non-transitory computer-accessible memory medium that stores:
application software configured to be deployed on and/or use first resources of a multiprocessor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and a high bandwidth interconnection network (IN) communicatively coupling the plurality of processing elements and the plurality of memories; and
program instructions executable by a processor to:
modify the application software that is desired to be tested to include testing code, thereby producing modified application software, wherein the testing code in the modified application software includes at least one auxiliary send statement, wherein the testing code is configured to use one or more second different resources of the MPA, wherein the one or more second different resources are not used by the application software, wherein the MPA executing the application software comprises a device under test (DUT);
wherein the modified application software executing on the MPA is configured to:
receive input data to stimulate the DUT;
generate first data in the DUT based on the input data;
execute a first send statement to provide the first data for use by the modified application software; and
execute an auxiliary send statement to provide the first data to a pin at an edge of the MPA using at least one of the one or more second resources of the MPA;

receive the first data resulting from the auxiliary send statement, wherein the first data are useable for analyzing the DUT.

13. A non-transitory computer-accessible memory medium that stores program instructions executable by a processor to:
analyze application software that desired to be tested, wherein the application software is configured to be deployed on first hardware resources of a multiprocessor array (MPA), wherein the MPA executing the application software comprises a device under test (DUT), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network (IN) communicatively coupling the plurality of processing elements and the plurality of memories, and wherein the MPA executing the application software in a real time at full operational speed comprises a device under test (DUT);
create test program code which is executable to configure hardware resources on the MPA to duplicate at least a subset of first data generated in the application software for analysis purposes;
execute an auxiliary send statement in the test program code to provide at least a subset of the

Assignees

• Coherent Logix Inc

Inventors

• Ellis Geoffrey N
• Beardslee John Mark
• Doerr Michael B
• Aguayo Ivan
• Dalio Brian A

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F9/45504

  Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F11/3688 Primary

  for test execution, e.g. scheduling of test suites · CPC title