Method for digital error correction for binary successive approximation analog-to-digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-9473162-B2
Application number	US-201414559178-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Dec 6, 2013
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a digital-to-analog converter with the analog input voltage and generating a second set of confirmed bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage. The first set of confirmed bits is independent of the second series of comparisons. The bits of the digital output code corresponding to the analog input voltage are generated based on the first set of confirmed bits, the second set of confirmed bits and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons.

First claim

The invention claimed is:

1. A method, comprising:
generating, using control logic, a first binary code having M+1 bits, M being an integer greater than 1;
generating, using control logic, a second binary code having N−M+1 bits, N being an integer greater than M;
carrying out a first binary decision using successive approximation register (SAR) processing on the bits of the first binary code by a first digital to analog conversion block of an analog to digital converter to generate a first voltage to be compared, using a comparator, with an input voltage to be converted;
generating a first segment of M+1 confirmed bits based on the comparison of the first voltage with the input voltage;
after the first segment of M+1 confirmed bits are generated, carrying out a second binary decision using SAR processing on the bits of the second binary code by a second digital to analog conversion block of the analog to digital converter to generate a second voltage to be compared with said input voltage;
generating a second segment of N−M+1 confirmed bits based on the comparison of the second voltage with the input voltage;
assigning a weight to a Least Significant Bit (LSB) of the first binary code;
assigning the same weight to a Most Significant Bit (MSB) of the second binary code;
providing a voltage shift using an adder between the comparison of the first voltage with the input voltage and the comparison of the second voltage with the input voltage, the voltage shift corresponding to half of the assigned weight in the analog-to-digital (A/D) converter; and
generating a digital output code based on the first segment of confirmed bits, the second segment of confirmed bits and a constant term corresponding to said voltage shift.

2. The method of claim 1 , wherein the digital output code is based on the following formula:
R<N: 0>= B′<M: 0>*2 N−M +C<N−M: 0>−2 N−M−1 ,

wherein
R<N:0> represents the generated digital output code;
B′<M:0> represents the first segment of confirmed bits;
C′<N−M:0> represents the second segment of confirmed bits, and:
X<y: 0>=Σ i=0 y X ( i )·2 i .

3. The method of claim 1 , comprising conveying said first binary code having M+1 bits on a first digital bus and conveying said second binary code having N−M+1 bits on a second digital bus separated from the first digital bus.

4. The method of claim 3 , comprising conveying said first segment of confirmed bits on the first digital bus and conveying said second segment of confirmed bits on the second digital bus.

5. The method according to claim 3 , wherein, during the conversion process, only one bit of the first digital bus is raised at a beginning of each tentative.

6. The method according to claim 1 , wherein generating the first and the second segments of confirmed bits comprises:
processing a logic signal representative of a result of comparison of a sum of said first and second voltages with the input voltage;
generating the first segment of M+1 confirmed bits and the second segment of N−M+1 confirmed bits as result of the processing step.

7. A method, comprising:
generating a first set of bits based on a first series of comparisons of an output of a digital-to-analog converter with an analog input voltage; and
after the first set of bits are generated:
generating a second set of bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage;
generating a third set of bits based on a third series of comparisons of the output of a digital-to-analog converter with the analog input voltage; and
generating bits of a digital output code corresponding to the analog input voltage based on the first set of bits, the second set of bits, the third set of bits, and a constant value representative of a voltage shift introduced in the digital-to-analog converter between the first series of comparisons and the second series of comparisons.

8. The method of claim 7 , comprising:
applying a first binary code having M+1 bits to a first digital-to-analog conversion circuit of the digital-to-analog converter, M being an integer greater than 1; and
applying a second binary code having N−M+1 bits to a second digital-to-analog conversion circuit of the digital-to-analog converter, N being an integer greater than M.

9. The method of claim 8 , comprising:
assigning a weight to a Least Significant Bit (LSB) of the first binary code; and
assigning the same weight to a Most Significant Bit (MSB) of the second binary code.

10. The method of claim 7 , comprising:
conveying said first set of bits on a first digital bus and conveying said second set of bits on a second digital bus separated from the first digital bus.

11. A system, comprising:
a digital-to-analog converter comprising first and second digital-to-analog conversion circuits, a voltage shifter and an adder;
a comparator having:
a first input terminal, which, in operation, receives an analog input voltage;
a second input terminal, which, in operation, receives an output of the digital-to-analog converter; and
an output terminal, which, in operation, outputs a first series of results of comparisons of the analog input voltage to the output of the digital-to-analog converter and a second series of results comparisons of the analog input voltage to the output of the digital-to-analog converter; and

control logic which, in operation:
generates a first binary code to input to the first digital-to-analog conversion circuit through a first digital bus;
generates at least a second binary code to input to the second digital to analog conversion circuit through a second digital bus;
generates a control signal which, in operation, causes the voltage shifter to apply a voltage shift to the adder between the first set of comparisons and the second set of comparisons;
generates a first set of bits based on the first series of results; and
generates a second set of bits based on the second series of results, wherein the second series of results are generated after the first set of bits are generated.

12. The system of claim 11 wherein said digital-to-analog converter comprises capacitive-resistive circuitry including capacitive upper arrays, capacitive lower arrays and a resistive sub-lower array.

13. The system of claim 11 , comprising post-processing logic which, in operation, generates bits of a digital output code corresponding to the analog input voltage based on the first set of bits, the second set of bits and a constant value representative of the voltage shift applied to the adder.

14. The system of claim 11 wherein the control logic, in operation,
assigns a weight to a Least Significant Bit (LSB) of the first binary code;
assigns the same weight to a Most Significant Bit (MSB) of the second binary code.

15. A device, comprising:
an input, which, in operation, receives results of comparisons of an analog input voltage to an output of a digital-to-analog converter; and
circuitry coupled to the input, which includes first and second digital-to-analog conversion circuits, a comparator, a voltage shifter, and an adder, and which, in operation:
generates a first set of bits based on a first series of comparisons of the output of the digital-to-analog converter with the analog input voltage;
after the first set of bits are generated, generates a second set of bits based on a second series of comparisons of the output of the digital-to-analog converter with the analog input voltage; and
generates bits of a digital output code corresponding to the analog input voltage based on the firs

Assignees

• St Microelectronics Int Nv

Inventors

• Girardi Francesca
• Minuti Alberto
• Nicollini Germano
• Zamprogno Marco

Classifications

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/765

  using a single level of switches which are controlled by unary decoded digital signals · CPC title

• H03M1/804

  with charge redistribution · CPC title