Digital-to-analog converter circuit

Patent metadata

Field	Value
Publication number	US-9548757-B2
Application number	US-201614991869-A
Country	US
Kind code	B2
Filing date	Jan 8, 2016
Priority date	Mar 11, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current. to the second sub digital to analog converter The digital to analog converter is configured to operate in a second mode for generating a ramp wave with a second bit level accuracy and, when in the second mode, the overlap adjustment circuit adds current to the second sub digital to analog converter. When in the second mode, the total current of the second sub digital to analog converter and the overlap converter is greater than one of the plurality of currents generated by the first sub digital to analog converter.

First claim

What is claimed is:

1. A digital to analog converter, comprising:
a current source for providing a master current;
a first sub digital to analog converter coupled to the current source, wherein the first sub digital to analog converter generates a plurality of currents;
a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter, wherein the second sub digital to analog converter generates a second plurality of currents;
an overlap adjustment circuit coupled with the second sub digital to analog converter, wherein the overlap adjustment circuit adds current, wherein
the digital to analog converter is configured to operate in a first mode for generating a first wave wherein the first wave has a first bit level accuracy and wherein the overlap adjustment circuit adds current to the second sub digital to analog converter, and
the digital to analog converter is configured to operate in a second mode for generating a second wave wherein the second wave has a second bit level accuracy and wherein the overlap adjustment circuit adds no current to the second sub digital to analog converter, and
the total current of the second sub digital to analog converter and the overlap converter is greater than each of the plurality of currents generated by the first sub digital to analog converter.

2. The digital to analog converter of claim 1 , wherein the currents of the first sub-digital to analog converter comprise the most significant bits and the currents of the second sub-digital to analog converter comprise the least significant bits.

3. The digital to analog converter of claim 2 , wherein the currents from the first sub-digital to analog converter comprise a plurality of currents each equal to the master current and the currents from the second sub-digital to analog converter comprise a second plurality of currents cumulatively equal to a single current generated by the first sub digital to analog converter.

4. The digital to analog converter of claim 2 , wherein the most significant bits comprise five most significant bits and the least significant bits comprise seven least significant bits.

5. The digital to analog converter of claim 4 , wherein the currents of the least significant bits are variably weighted.

6. The digital to analog converter of claim 5 , wherein the currents of the least significant bits are binary weighted currents.

7. The digital to analog converter of claim 2 , wherein the current of one most significant bit is greater than or equal to the current of all of the least significant bits.

8. The digital to analog converter of claim 1 , wherein the first wave first bit level accuracy is a twelve bit level accuracy.

9. A frequency modulated continuous wave transceiver with a multiple mode digital to analog converter, the transceiver comprising:
an analog to digital converter;
a digital to analog converter coupled to the analog to digital converter, the digital to analog converter further comprising:
a current source for providing a master current;
a first sub digital to analog converter coupled to the current source, wherein the first sub digital to analog converter generates a plurality of currents;
a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter, wherein the second sub digital to analog converter generates a second plurality of currents;
an overlap adjustment circuit coupled with the second sub digital to analog converter, wherein the overlap adjustment circuit adds current;

a voltage controlled oscillator coupled to the digital to analog converter, wherein;
the digital to analog converter is configured to operate in a first mode for generating a first wave wherein the first wave has a first bit level accuracy and wherein the overlap adjustment circuit adds current to the second sub digital to analog converter, and
the digital to analog converter is configured to operate in a second mode for generating a second wave wherein the second wave has a second bit level accuracy and wherein the overlap adjustment circuit adds no current to the second sub digital to analog converter, and
the total current of the second sub digital to analog converter and the overlap converter is greater than each of the plurality of currents generated by the first sub digital to analog converter.

10. The transceiver of claim 9 , wherein the digital to analog converter generates a falling ramp signal in the first mode.

11. The transceiver of claim 10 , wherein the falling ramp signal has a 12 bit level accuracy.

12. The transceiver of claim 9 , wherein the digital to analog converter generates a sine wave for transmission to the analog to digital converter in the second mode.

13. The transceiver of claim 12 , wherein the analog to digital converter comprises continuous time sigma delta analog to digital converters.

14. The transceiver of claim 13 , wherein the continuous time sigma delta analog to digital converters receive the generated sine wave as an element of an internal check.

15. The transceiver of claim 12 , wherein the generated sine wave bit level accuracy is a ten bit level accuracy.

16. A method of transitioning from all of the least significant bits to a most significant bit in a digital to analog converter, the method comprising the steps of:
generating a current for each most significant bit;
generating a second current to each of a first set of the least significant bits and generating a third current to a second set of the least significant bits, wherein the sum of the second and third currents is not more than the current for a most significant bit;
determine the current for each most significant bit;
identify a largest current for one of the most significant bits;
determine the total current to all least significant bits;
identify a current difference between the largest current for one of the most significant bits and the current to all the least significant bits;
generating an overlap current to add to the total current of the least significant bits wherein the overlap current exceeds the current difference;
wherein the total current of the least significant bits with the overlap current is greater than the current from a single most significant bit.

17. The method of claim 16 , wherein the current for each most significant bit is equal.

18. The method of claim 16 , wherein each second current for the first set of least significant bits is equal and the third current of the second set of the least significant bits is binary weighted.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Kabir Mohammad Nizam
• Braswell Brandt
• Hoseini Mariam

Classifications

• G01S7/35

  Details of non-pulse systems · CPC title

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/745

  with weighted currents · CPC title

• G01S7/352

  Receivers · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title