Semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9472668-B2
Application number	US-201514799879-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Jul 21, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second regions; providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate; and forming first trenches in the first region at both sides of the first gate structure. The method further includes forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer; forming second trenches in a second region at both sides of the second gate structure; and forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer.

First claim

What is claimed is:

1. A semiconductor fabrication method, comprising:
providing a semiconductor substrate having first regions and second regions;
providing a first gate structure on a first region of the semiconductor substrate, and a second gate structure on a second region of the semiconductor substrate;
forming first trenches in the first region at both sides of the first gate structure;
forming a first stress layer in the first trenches and a first bumping stress layer on the first stress layer, wherein the first bumping stress layer is doped with first dopants including Al, In, or a combination thereof;
forming second trenches in a second region at both sides of the second gate structure;
forming a second stress layer in the second trenches and a second bumping stress layer on the second stress layer, wherein the second bumping stress layer is doped with second dopants;
forming a metal layer on the first bumping stress layer and the second bumping stress layer; and
performing a thermal annealing process such that the metal layer reacts with the first bumping stress layer to form a first silicide layer on the first bumping stress layer and the metal layer reacts with the second bumping stress layer to form a second silicide layer on the second bumping stress layer.

2. The method according to claim 1 , wherein the second dopants are Al, Se, Sb, Te, or a combination thereof.

3. The method according to claim 2 , wherein a doping concentration of the first dopants is about 1E15 cm −3 to about 1E17 cm −3 , and a doping concentration of the second dopants is about 1E15 cm −3 to about 1E17 cm −3 .

4. The method according to claim 3 , wherein a doping depth of the second dopants is less than a doping depth of the first dopants.

5. The method according to claim 4 , wherein:
after the first silicide layer and the second silicide layer are formed, each of the first silicide layer and the first bumping stress layer under the first silicide layer includes a portion of the first dopants, and second dopants are entirely confined in the second silicide layer.

6. The method according to claim 1 , wherein the steps for forming the first trenches, the first stress layer, and the first bumping stress layer include:
forming a first mask layer to cover the second regions and first gate structures before forming the first trenches;
using the first mask layer as an etch mask for etching portions of the first regions at both sides of each first gate structure to form first trenches;
using a selective deposition process to form the first stress layer to fill up the first trenches; and
using a selective deposition process to form the first bumping stress layer on the first stress layer, wherein a gas containing first dopants is introduced into the selective deposition process to dope the first bumping stress layer with first dopants.

7. The method according to claim 6 , wherein the step for forming the first trenches include:
etching portions of the first region at both sides of each first gate structure by using a dry etch process to form openings; and
etching the openings by using an isotropic wet etch process to form first trenches, wherein a sidewall of a first trench has a “Σ” shape.

8. The method according to claim 1 , wherein the steps for forming the second trenches, the second stress layer, and the second bumping stress layer include:
forming a second mask layer to cover the first regions and second gate structures before forming the second trenches;
using the second mask layer as an etch mask to etch portions of the second regions at both sides of each second gate structure to form second trenches;
using a selective deposition process to form the second stress layer to fill up the second trenches; and
using a selective deposition process to form the second bumping stress layer on the second stress layer, wherein a gas containing second dopants is introduced into the selective deposition process to dope the second bumping stress layer with second dopants.

9. The method according to claim 8 , wherein portions of the second region at both sides of each second gate structure are etched by using a dry etch process to form second trenches.

10. The method according to claim 8 , wherein a doping depth of the second dopants is less than a total thickness of the second bumping stress layer.

11. The method according to claim 8 , wherein after a thickness of the second bumping stress layer reaches a certain portion of the total thickness of the second bumping stress layer by the selective deposition process, a gas containing second dopants is introduced into the selective deposition process to dope the second bumping stress layer with second dopants.

12. The method according to claim 1 , wherein, before forming the first trenches and the second trenches, the method further includes:
doping portions of a first region at both sides of each first gate structure with a first light ion implantation process and a first pocket ion implantation process; and
doping portions of a second region at both sides of each second gate structure with a second light ion implantation process and a second pocket ion implantation process.

13. The method according to claim 1 , wherein the first stress layer and the first bumping stress layer are doped with P-type dopants.

14. The method according to claim 1 , wherein the second stress layer and the second bumping stress layer are doped with N-type dopants.

15. The method according to claim 1 , wherein the metal layer is made of Ti, Al, La, Zn, Ni, or a combination thereof.

16. The method according to claim 15 , wherein a thermal annealing temperature of the thermal annealing process is about 250 degrees Celsius to about 800 degrees Celsius; and a thermal annealing time is about 30 seconds to about 90 seconds.

17. A semiconductor device, comprising:
a semiconductor substrate having first regions;
a first gate structure on a first region of the semiconductor substrate;
a first stress layer in a first region and at both sides of each first gate structure;
a first bumping stress layer on the first stress layer, above a top surface of the semiconductor substrate, and doped with first dopants; and
a first silicide layer on the first bumping stress layer and over the top surface of the semiconductor substrate, wherein the first dopants include Al, In, or a combination thereof and are distributed in the first silicide layer and the first bumping stress layer.

18. The semiconductor device according to claim 17 , wherein the first stress layer and the first bumping stress layer are made of SiGe.

19. The method according to claim 1 , wherein the first bumping stress layer and the second bumping stress layer are doped by an in-situ doping process.

20. The method according to claim 5 , wherein carbon ions prevent diffusion of the second dopants such that the second dopants do not diffuse outward beyond the bumping stress layer during the formation of the second silicide layer by thermal annealing and the second dopants are entirely confined in the second silicide layer.

21. The semiconductor device according to claim 17 , wherein:
the semiconductor substrate further includes second regions,
a second gate structure is on a second region of the semiconductor substrate,
a second stress layer is in a second region of the semiconductor substrate and at both sides of each second gate structure,
a second bumping stress layer is on the second stress layer, above a top surfa

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xie Xinyun

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3442

  N-type · CPC title