Semiconductor device and method of forming wire bondable fan-out EWLB package

Patent metadata

Field	Value
Publication number	US-9472533-B2
Application number	US-201414548064-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Nov 20, 2013
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
depositing a first encapsulant over the first semiconductor die;
forming an interconnect structure over the first semiconductor die and first encapsulant;
disposing a second semiconductor die over the first semiconductor die opposite the interconnect structure;
forming an opening in the first encapsulant adjacent to the first semiconductor die and over the interconnect structure; and
forming a bond wire in the opening in the first encapsulant and coupled between the second semiconductor die and interconnect structure.

2. The method of claim 1 , further including depositing a second encapsulant over the second semiconductor die and bond wire.

3. The method of claim 1 , further including disposing a modular interconnect structure adjacent to the first semiconductor die.

4. The method of claim 3 , further including:
depositing the first encapsulant over the modular interconnect structure; and
forming the opening extending to the modular interconnect structure.

5. The method of claim 1 , further including forming the opening extending through the first encapsulant to the interconnect structure.

6. A semiconductor device, comprising:
a first semiconductor die;
a first encapsulant deposited over and covering a side surface of the first semiconductor die including an opening formed through the encapsulant;
a first interconnect structure formed over the first encapsulant and first semiconductor die and extending over the opening;
a second semiconductor die disposed over the first semiconductor die and first encapsulant; and
a bond wire extending from the second semiconductor die and through the opening in the first encapsulant to couple the second semiconductor die to the first interconnect structure.

7. The semiconductor device of claim 6 , further including a modular interconnect structure including a conductive via disposed in the first encapsulant.

8. The semiconductor device of claim 6 , further including a second encapsulant deposited over the second semiconductor die and bond wire.

9. The semiconductor device of claim 6 , further including a cap disposed over an active region of the second semiconductor die.

10. The semiconductor device of claim 6 , wherein the second semiconductor die includes a microelectromechanical system.

11. The semiconductor device of claim 6 , wherein the bond wire is mechanically bonded to the first semiconductor die and first interconnect structure.

12. A semiconductor device comprising:
a first semiconductor die including an active surface;
a first encapsulant disposed over the first semiconductor die opposite the active surface, the first encapsulant including an opening;
a bond wire mechanically bonded to the active surface of the first semiconductor die and extending through the opening in the first encapsulant; and
a modular interconnect structure including a conductive via disposed in the first encapsulant.

13. The semiconductor device of claim 12 , further including a second semiconductor die disposed in the encapsulant over the first semiconductor die.

14. The semiconductor device of claim 12 , further including a lid formed over the first semiconductor die.

15. The semiconductor device of claim 13 , further including a first interconnect structure formed over the encapsulant opposite the first semiconductor die, wherein the second semiconductor die is coupled to the first semiconductor die through the first interconnect structure and bond wire.

16. The semiconductor device of claim 13 , wherein the first semiconductor die is mounted directly to the second semiconductor die with a die attach adhesive.

17. A method of making a semiconductor device, comprising:
depositing an encapsulant over a substrate;
disposing a first semiconductor die over a first surface of the encapsulant with an active surface of the first semiconductor die oriented away from the encapsulant;
forming a first interconnect structure over a second surface of the encapsulant opposite the first surface;
forming an opening through the encapsulant; and
forming a second interconnect structure extending from the first semiconductor die to the first interconnect structure through the opening of the encapsulant.

18. The method of claim 17 , further including disposing a second semiconductor die on the substrate prior to depositing the encapsulant.

19. The method of claim 18 , further including disposing a modular interconnect structure on the substrate prior to depositing the encapsulant.

20. The method of claim 17 , further including disposing a cap over an active region of the first semiconductor die.

21. The method of claim 17 , wherein forming the second interconnect structure includes forming a bond wire.

22. The method of claim 21 , further including forming a conductive layer in the opening prior to forming the bond wire.

23. The method of claim 17 , wherein the active surface of the first semiconductor die includes a sensor.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Pendse Rajendra D

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title