Leadframe area array packaging technology

Patent metadata

Field	Value
Publication number	US-9472532-B2
Application number	US-201514678840-A
Country	US
Kind code	B2
Filing date	Apr 3, 2015
Priority date	Nov 19, 2012
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package comprising:
a. providing a carrier strip having top and bottom surfaces;
b. applying a layer of polymer material on the top surface of the carrier strip;
c. fabricating interconnects on a top surface of the layer of polymer material;
d. assembling a package;
e. decoupling the carrier strip from the package;
f. forming a plurality of openings in the layer of polymer material;
g. applying suitable material in the plurality of openings; and
h. singulating the package from other packages.

2. The method of claim 1 , wherein the carrier strip is of copper base.

3. The method of claim 1 , wherein the carrier strip is of glass.

4. The method of claim 1 , wherein the polymer material is liquid.

5. The method of claim 1 , wherein the polymer material is non-liquid.

6. The method of claim 1 , wherein the polymer material is solder resist.

7. The method of claim 1 , wherein fabricating interconnects include:
a. laminating a metal foil; and
b. applying a layer of dry film resist; and
c. forming patterns on the layer of dry film resist to form the interconnects.

8. The method of claim 7 , wherein the metal foil is Cu foil and has a thickness of 5-50 μm.

9. The method of claim 1 , wherein fabricating interconnects include:
a. forming trenches in the layer of polymer material; and
b. filling the trenches with a material to form the interconnects.

10. The method of claim 9 , wherein the material is one of Cu, Ag, and NiPdAu.

11. The method of claim 1 , wherein fabricating interconnects include:
a. laminating a photomask on top of the layer of polymer material;
b. exposing patterns; and
c. plating up the interconnects.

12. The method of claim 1 , wherein the interconnects are plated with one of Cu, Ag, and NiPdAu.

13. The method of claim 1 , wherein assembling a package includes:
a. coupling a die to at least a portion of the interconnects;
b. wirebonding the die to the interconnects; and
c. encapsulating the die, the interconnects and wirebonds.

14. The method of claim 13 , wherein the die is coupled to the at least a portion of the interconnects using one of non-conductive epoxy, a solder mask at a die flag area, and a die attach pad.

15. The method of claim 1 , wherein assembling a package includes:
a. coupling a die to at least a portion of the interconnects via conductive pillars; and
b. encapsulating the die, the conductive pillars and the interconnects.

16. The method of claim 1 , wherein decoupling the carrier strip includes dry/wet etching the carrier strip from the layer of polymer material.

17. The method of claim 1 , wherein decoupling the carrier strip includes debonding the carrier strip from the layer of polymer material.

18. The method of claim 1 , wherein creating a plurality of openings includes exposing the interconnects at predetermined locations.

19. The method of claim 1 , wherein applying suitable material includes using one of solder printing and solder ball mounting in the plurality of openings.

20. The method of claim 1 , wherein applying suitable material includes performing one of the forming conductive pillars, electroless plating, incorporating immersion tin, and applying solderability preservatives.

21. The method of claim 1 , further comprising forming at least one openings in the layer of polymer material.

22. The method of claim 1 , wherein the interconnects are fabricated on the top surface of the layer of polymer material by forming trenches in the layer of polymer material, wherein the trenches only extend part way through the layer of polymer material.

23. A method of fabricating a semiconductor package comprising:
a. obtaining a carrier strip;
b. applying a layer of solder resist on a surface of the carrier strip;
c. fabricating an area array of I/O contacts on a top surface of the layer of solder resist, wherein fabricating includes:
i. laminating a Cu foil on a top surface of the layer of solder resist; and
ii. interconnect patterning using dry film resist and etching process;

d. assembling a package; and
e. removing the carrier strip from the layer of solder resist.

24. A method of fabricating a semiconductor package comprising:
a. providing a strip having a base layer, a layer of polymer material on a top surface of the base layer and interconnects on a top surface of the layer of the polymer material;
b. assembling a package by coupling a die with one or more of the interconnects;
c. removing the base layer from the package;
d. forming a plurality of openings in the layer of polymer material;
e. applying a metallic filling material in the plurality of the openings; and
f. singulating the package from other packages.

Assignees

• United Test And Assembly Center Ltd
• Utac Headquarters Pte Ltd

Inventors

• Dimaano Jr Antonio Bambalan
• Suthiwongsunthorn Nathapong
• Yang Yong Bo

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title