Codec engine with inline image processing

Patent metadata

Field	Value
Publication number	US-9471995-B2
Application number	US-201414154292-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Jan 14, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A video device includes a codec engine to process video data to generate a stream of pixel blocks representing a picture of a sequence of pictures represented by the video data, an image processing module to receive the stream of pixel blocks via a local path between the codec engine and the image processing module and to perform at least one image processing function for the picture using pixel blocks of the stream of pixel blocks received via the local path to generate image processing result data representative of the picture. The video device further includes a storage interface coupleable to a storage component, the storage interface to provide the image processing result data for storage at the storage component.

First claim

What is claimed is:

1. A video device comprising:
a die implementing:
a codec engine to process video data to generate a stream of pixel blocks during transcoding of the video data by the codec engine, the stream of pixel blocks representing a picture of a sequence of pictures represented by the video data; and
an image processing module to receive the stream of pixel blocks via a local path of the die between the codec engine and the image processing module and to perform at least one image analysis function using pixel blocks of the stream of pixel blocks received via the local path to generate image metadata describing one or more analyzed characteristics of the picture, wherein the image processing module performs the at least one image analysis function in parallel with the codec engine generating the stream of pixel blocks; and

a storage interface coupleable to a storage component, the storage interface to provide the image metadata for storage at the storage component.

2. The video device of claim 1 , wherein the local path comprises:
a first cache having an input coupled to an output of the codec engine and an output coupled to the image processing module, the first cache to temporarily store a subset of pixel blocks of the stream of pixel blocks.

3. The video device of claim 1 , wherein the local path comprises:
an on-chip bus connecting the codec engine and the image processing module.

4. The video device of claim 1 , further comprising:
a memory interface coupleable to a memory external to the die, the memory interface to provide the stream of pixel blocks for storage at the memory.

5. The video device of claim 4 , wherein:
the storage component comprises the memory external to the die.

6. A method comprising:
processing video data at a codec engine of a die of a video device to generate a stream of pixel blocks during transcoding of the video data, the stream of pixel blocks representing a picture of a sequence of pictures represented by the video data;
providing the stream of pixel blocks to an image processing module of the die of the video device via a local path of the die between the codec engine and the image processing module;
performing an image analysis function at the image processing module using pixel blocks received via the local path to generate image metadata describing one or more analyzed characteristics of the picture, wherein the image processing module performs the image analysis function in parallel with the codec engine generating the stream of pixel blocks; and
storing the image metadata at a storage component.

7. The method of claim 6 , further comprising:
storing the stream of pixel blocks at the storage component in association with the image metadata.

8. The method of claim 6 , wherein providing the stream of pixel blocks to the image processing module via a local path comprises one of: temporarily storing pixel blocks of the stream at a cache accessible by the image processing module; and providing the stream of pixel blocks to the image processing module via an on-chip bus connecting the codec engine and the image processing module.

Assignees

• Vixs Systems Inc

Inventors

• Laksono Indra
• Young Eric
• Yeh Chun-Chin

Classifications

• H04N19/40

  using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream · CPC title

• G09G5/39

  Control of the bit-mapped memory · CPC title

• H04N7/012

  Conversion between an interlaced and a progressive signal (for graphics images G09G2310/0229) · CPC title

• H04N19/85

  using pre-processing or post-processing specially adapted for video compression · CPC title

• G09G5/363 Primary

  Graphics controllers · CPC title