Designing and manufacturing methods of TFT LCD array positioning mark

Patent metadata

Field	Value
Publication number	US-9470973-B2
Application number	US-201414368295-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Apr 1, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

The present invention relates to TFT LCD array positioning mark designing and manufacturing methods. The TFT LCD array positioning mark manufacturing method includes: (1) forming a passivation layer of TFT LCD array; (2) providing a mask corresponding to the passivation layer, the mask comprising a passivation layer positioning mark that corresponds to a metal positioning mark of the TFT LCD array; and (3) using the mask to form a corresponding passivation layer positioning mark on the passivation layer. The TFT LCD array positioning mark designing method includes: forming a passivation layer positioning mark on a passivation layer of an TFT LCD array to correspond to a metal positioning mark of the TFT LCD array. The present invention provides TFT LCD array positioning mark designing and manufacturing method, wherein a passivation layer positioning mark that is designed and manufactured with them shows a pattern that is more stable and is not susceptible to deformation so as to eliminate the problem of positioning failure of the metal positioning mark occurring in the cell and module processes.

First claim

What is claimed is:

1. A method, comprising the following steps:
(1) providing a substrate;
(2) forming a gate on the substrate through sputtering a metal layer and patterning the metal layer with a first-round masking operation by using a first mask;
(3) forming a gate insulation layer on the gate through chemical vapor deposition;
(4) forming an oxide semiconductor layer on the gate insulation layer through sputtering and a second-round masking operation by using a second mask;
(5) forming a first protection layer that serves as an etch stop layer on the oxide semiconductor layer through chemical vapor deposition, forming a metal layer on the first protection layer through sputter operation, and forming a data line electrode through a third-round masking operation by using a third mask;
(6) forming a second protection layer that serves as a passivation layer on the first protection layer and the data line electrode through chemical vapor deposition and forming first, second, and third bridging holes in the passivation layer through a fourth-round masking operation by using a fourth mask such that the first bridging hole is formed on the data line electrode and the second and third bridging holes are respectively formed on two ends of the oxide semiconductor layer; and
(7) forming a transparent conductive layer on the second protection layer through sputtering and patterning the transparent conductive layer with a fifth-round masking operation by using a fifth mask such that a first portion of the transparent conductive layer is electrically connected to the data line electrode and one of the two ends of the oxide semiconductor layer through the first and second bridging holes and a second portion of the transparent conductive layer is electrically connected to the other one of the two ends of the oxide semiconductor layer through the third bridging hole for formation of a pixel electrode;
wherein the first mask comprises a pattern that forms the gate and a mark pattern that forms a metal positioning mark on the metal layer; and
wherein the fourth mask comprises a pattern that forms the first, second, and third bridging holes in the passivation layer and the fourth mask also comprises a mark pattern that is formed in a predetermined location of the fourth mask for forming a passivation layer positioning mark in the passivation layer during the fourth-round masking operation such that the passivation layer positioning mark corresponds in position to the metal positioning mark formed on the metal layer with which the gate is formed.

2. The method as claimed in claim 1 , wherein the passivation layer comprises a silicon nitride layer.

3. The T method as claimed in claim 1 , wherein the passivation layer positioning mark is of a cruciform shape.

4. The method as claimed in claim 3 , wherein the metal positioning mark is of a rectangular shape.

5. The method as claimed in claim 1 , wherein the passivation layer positioning mark comprises a hollow pattern.

6. The method as claimed in claim 1 , wherein the passivation layer positioning mark comprises a solid pattern.

7. The method as claimed in claim 1 further comprising a step of conducting a cell process and a module process in which additional masks are used, wherein alignment of the additional masks is achieved with the passivation layer positioning mark.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Fu Yanfeng

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title