Flip-chip linear power amplifier with high power added efficiency

Patent metadata

Field	Value
Publication number	US-9467940-B2
Application number	US-201213673612-A
Country	US
Kind code	B2
Filing date	Nov 9, 2012
Priority date	Nov 11, 2011
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.

First claim

What is claimed is:

1. A flip-chip apparatus comprising:
a radio-frequency (RF) signal path having a node driven by at least one circuit element formed on a flip-chip die;
a first termination circuit electrically coupled to the RF signal path and configured to match an impedance at a fundamental frequency of a signal at the node, the first termination circuit including a first circuit element that is external to the flip-chip die; and
a second termination circuit electrically coupled to the RF signal path and separate from the first termination circuit, the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the signal at the node, the second termination circuit including a second circuit element that is external to the flip-chip die, the second circuit element being a capacitor, and the second circuit element and the first circuit element being electrically connected to the flip-chip die by way of different bumps.

2. The apparatus of claim 1 wherein the at least one circuit element includes a power amplifier.

3. The apparatus of claim 2 wherein the node is connected to an output of the power amplifier.

4. The apparatus of claim 2 wherein the node is connected to an input of the power amplifier.

5. The apparatus of claim 1 wherein the harmonic frequency includes a second harmonic frequency of the signal.

6. The apparatus of claim 1 further comprising a fundamental load line that includes the first termination circuit.

7. The apparatus of claim 1 wherein at least a portion of the first termination circuit and at least a portion of the second termination circuit are implemented on a flip-chip packaging substrate.

8. The apparatus of claim 7 wherein the signal path is implemented on the flip-chip die in communication with the flip-chip packaging substrate.

9. The apparatus of claim 7 wherein the packaging substrate includes a laminate substrate.

10. The apparatus of claim 7 wherein the first circuit element is a capacitor implemented on the packaging substrate.

11. The apparatus of claim 1 further comprising a third termination circuit separate from both the first termination circuit and the second termination circuit, the third termination circuit configured terminate at a phase corresponding to another harmonic frequency of the signal at the node.

12. The apparatus of claim 1 wherein the at least one circuit element includes a gallium arsenide bipolar transistor, a collector of the gallium arsenide bipolar transistor being configured to drive the node.

13. The apparatus of claim 1 wherein the first termination circuit includes a first inductive circuit element and a first capacitive circuit element, the first circuit element being either the first inductive circuit element or the first capacitive circuit element.

14. The apparatus of claim 13 wherein the second termination circuit includes a second inductive circuit element.

15. The apparatus of claim 1 wherein the node is included in a path between a first power amplifier stage and a second power amplifier stage.

16. A multi-chip module comprising:
a flip-chip power amplifier die including one or more power amplifiers configured to amplify an input signal and to generate an amplified output signal; and
an output matching network electrically coupled to the one or more power amplifiers, the output matching network including a first termination circuit configured to match an impedance at a fundamental frequency of the amplified output signal, the first termination circuit including a first circuit element external to the flip-chip power amplifier die; and a second termination circuit separate from the first termination circuit, the second termination circuit including a second circuit element external to the flip-chip power amplifier die, the second circuit element being electrically connected to the flip-chip power amplifier die by way of a second bump and the first circuit element being electrically connected to the flip-chip power amplifier die by way of a first bump, the first bump and the second bump being different bumps, and the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the amplified output signal.

17. The multi-chip module of claim 16 wherein the flip-chip power amplifier die includes a GaAs device and at least a portion of the output matching network is embodied on a flip-chip packaging substrate.

18. The multi-chip module of claim 16 wherein the output matching network is configured to cause an amount of energy of the amplified output signal converted to energy corresponding to a harmonic frequency component of the amplified output signal to be reduced.

19. A mobile device comprising:
a battery configured to power the mobile device;
a flip-chip power amplifier die including one or more power amplifiers configured to amplify a radio frequency (RF) input signal and to generate an amplified RF signal;
an antenna configured to transmit the amplified RF signal; and
an output matching network electrically coupled to the one or more power amplifiers, the output matching network including a first termination circuit configured to match an impedance at a fundamental frequency of the amplified RF signal, the first termination circuit including a first circuit element external to the flip-chip power amplifier die; and a second termination circuit separate from the first termination circuit, the second termination circuit including a second circuit element external to the flip-chip power amplifier die, the second circuit element being electrically connected to the flip-chip power amplifier die by way of a second bump and the first circuit element being electrically connected to the flip-chip power amplifier die by way of a first bump, the first bump and the second bump being different bumps, and the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF signal so as to extend an amount of time for the battery to discharge.

20. The mobile device of claim 19 configured to communicate using at least one of a 3G communications standard and a 4G communications standard.

Assignees

• Skyworks Solutions Inc

Inventors

• Zhang Guohao
• Modi Hardik Bhupendra
• Joshi Jaydutt Jagdish
• Vijayakumar Bhuvaneshwaran
• Hoang Dinhphuoc Vu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title