Apparatus and methods for power amplifiers

Patent metadata

Field	Value
Publication number	US-9231533-B2
Application number	US-201514728881-A
Country	US
Kind code	B2
Filing date	Jun 2, 2015
Priority date	Nov 4, 2011
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6Ω and about 10Ω. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a power amplifier die on the substrate, the power amplifier die including a power amplifier configured to receive a radio frequency signal having a fundamental frequency and to provide an amplified radio frequency signal at an output; and
an impedance matching network on the substrate and electrically connected to the output of the power amplifier, the impedance matching network configured to provide a load line impedance between about 6Ω and about 10Ω at the fundamental frequency, the impedance matching network including a fundamental matching circuit and a harmonic termination circuit, the fundamental matching circuit and the termination circuit having separate electrical connections to the power amplifier die.

2. The apparatus of claim 1 wherein the harmonic termination circuit includes a capacitor external to the power amplifier die.

3. The apparatus of claim 2 further comprising a first trace on the substrate and a second trace on the substrate, the fundamental matching circuit including a second capacitor external to the power amplifier die and electrically connected to the second trace, and the capacitor being electrically connected to the first trace.

4. The apparatus of claim 1 wherein impedance matching network is configured such that the load line impedance is about 8Ω at the fundamental frequency.

5. The apparatus of claim 1 further comprising an envelope tracker configured to generate a power supply voltage for the power amplifier.

6. The apparatus of claim 1 further comprising a bias die on the substrate, the bias die configured to provide a bias signal to the power amplifier.

7. An apparatus comprising:
a power amplifier configured to receive a radio frequency signal having a fundamental frequency and to provide an amplified radio frequency signal at an output; and
an impedance matching network electrically coupled to the output of the power amplifier and configured to provide a load line impedance between about 6Ω and about 10Ω at the fundamental frequency, the impedance matching network including a fundamental matching circuit and a harmonic termination circuit.

8. The apparatus of claim 7 further comprising an envelope tracker configured to generate a power supply voltage for the power amplifier.

9. The apparatus of claim 8 further comprising a bias network including a choke inductor in an electrical path between the envelope tracker and the power amplifier, and the bias network further including a bypass capacitor electrically connected between the power supply voltage and a ground node.

10. The apparatus of claim 9 wherein the bypass capacitor has a capacitance in a range from about 50 pF to about 200 pF.

11. The apparatus of claim 7 wherein the power amplifier is implemented on a power amplifier die, and the fundamental matching circuit and the harmonic termination circuit each has a separate electrical connection to the power amplifier die.

12. The apparatus of claim 7 wherein the power amplifier is implemented on a power amplifier die, the fundamental matching circuit including a first capacitor external to the power amplifier die, and the harmonic termination circuit including a second capacitor external to the power amplifier die.

13. The apparatus of claim 12 wherein the first capacitor and the second capacitor have separate electrical connections to the power amplifier die.

14. The apparatus of claim 12 wherein a bond wire provides an electrical connection between the first capacitor and the power amplifier die, and the bond wire is not in an electrical path between the second capacitor and the power amplifier die.

15. The apparatus of claim 12 wherein the first capacitor and the second capacitor are electrically connected to the power amplifier die by way of different bond wires.

16. The apparatus of claim 7 wherein the harmonic termination circuit is configured to terminate a second harmonic of the fundamental frequency.

17. The apparatus of claim 7 wherein the harmonic termination circuit is configured to terminate a third harmonic of the fundamental frequency, and the impedance matching network is configured to provide no harmonic termination for even harmonic frequencies.

18. The apparatus of claim 7 wherein the impedance matching network includes another harmonic termination circuit.

19. The apparatus of claim 7 wherein impedance matching network is configured such that the load line impedance is about 8Ω at the fundamental frequency.

20. An apparatus comprising:
an impedance matching network configured to receive a radio frequency signal having a fundamental frequency and to provide a load line impedance between about 6Ω and about 10Ω at the fundamental frequency, the impedance matching network including a fundamental matching circuit and a harmonic termination circuit;
an envelope tracker configured to provide a power supply voltage; and
a biasing network electrically connected to the envelope tracker and operatively associated with the impedance matching network, the biasing network configured to provide a bypass capacitance in the range of about 50 pF to about 200 pF.

Assignees

• Skyworks Solutions Inc

Inventors

• Zhang Guohao
• Modi Hardik Bhupendra
• Khesbak Sabah

Classifications

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H03F2200/465

  Power sensing · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F1/0222

  by using a signal derived from the input signal · CPC title