Successive approximation AD converter
US-8947290-B2 · Feb 3, 2015 · US
US9467159B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9467159-B1 |
| Application number | US-201514930673-A |
| Country | US |
| Kind code | B1 |
| Filing date | Nov 3, 2015 |
| Priority date | Jun 11, 2015 |
| Publication date | Oct 11, 2016 |
| Grant date | Oct 11, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An analog-to-digital converting device includes a converting module, for sampling an analog input voltage according to a plurality of sampling signals to generate a comparing voltage and generating a comparing signal according to the comparing voltage, wherein the converting module comprises a plurality of capacitors and each of the plurality of capacitors couples between one of the plurality sampling signals and the comparing voltage; a control module, for adjusting the plurality of sampling signals according to the comparing signal, to generate a digital signal corresponding to the analog input voltage, wherein a plurality of bits of the digital signal are respectively corresponding to the capacitances of the plurality of capacitors; and a calibration module, for adjusting the capacitances of the plurality of capacitors according to the digital signal.
Opening claim text (preview).
What is claimed is: 1. An analog-to-digital converting device, comprising: a converting module, for sampling an analog input voltage to generate a comparing voltage according to a plurality of sampling signals and generating a comparing signal according to the comparing voltage, wherein the converting module comprises a plurality of capacitors and each of the plurality of capacitors couples between one of the plurality sampling signals and the comparing voltage; a control module, for adjusting the plurality of sampling signals according to the comparing signal, to generate a digital signal corresponding to the analog input voltage, wherein a plurality of bits of the digital signal respectively are corresponding to capacitances of the plurality of capacitors except the least significant bit among the plurality of bits; and a calibration module, for adjusting the capacitances of a first capacitor among the plurality of capacitors when a number of times that the digital signal equals a pattern exceeds a threshold; wherein a first bit among the plurality of bits in the pattern is different from the bits between the first bit and the least significant bit of the plurality of bits in the pattern and the first bit is corresponding to the first capacitor. 2. The analog-to-digital converting device of claim 1 , wherein the first bit is different from the least significant bit of the plurality of bits in the pattern, and the calibration module decreases a capacitance of a first capacitor corresponding to the first bit among the plurality of bits when the number of times that the digital signal equals the pattern exceeds the threshold. 3. The analog-to-digital converting device of claim 1 , wherein the first bit is the same as the least significant bit of the plurality of bits in the pattern, and the calibration module increases a capacitance of a first capacitor corresponding to the first bit among the plurality of bits when the number of times that the digital signal equals the pattern exceeds the threshold. 4. The analog-to-digital converting device of claim 1 , wherein the plurality of capacitors comprise at least one variable capacitor and at least one fixed capacitor and the calibration module adjusts a capacitance of the at least one variable capacitor according to the digital signal. 5. The analog-to-digital converting device of claim 1 , wherein the comparing voltage is a voltage difference between a first input end and a second input end of the converting module. 6. The analog-to-digital converting device of claim 1 , wherein the comparing voltage is a voltage of an input end of the converting module. 7. The analog-to-digital converting device of claim 1 , further comprising: a storage unit, for storing the adjusted capacitances of the plurality of capacitors. 8. A calibration method for an analog-to-digital converting device, which converts an analog input voltage to a digital signal with a plurality of bits and the bits other than the least significant bit among the plurality of bits are corresponding to capacitances of a plurality of capacitors in the analog-to-digital converting device, the calibration method comprising: detecting a number of times that the digital signal equals a pattern, wherein a first bit among the plurality of bits in the pattern is different from the bits between the first bit and the least significant bit among the plurality of bits in the pattern; and adjusting a capacitance of a first capacitor corresponding to the first bit when the number of times that the digital signal equals the pattern exceeds a threshold. 9. A calibration module for an analog-to-digital converting device, which converts an analog input voltage to a digital signal with a plurality of bits and the bits other than the least significant bit among the plurality of bits are corresponding to capacitances of a plurality of capacitors in the analog-to-digital converting device, the calibration module comprising: a processing unit; and a storage unit, for storing a program code instructing the processing unit perform the following steps: detecting a number of times that the digital signal equals a pattern, wherein a first bit among the plurality of bits in the pattern is different from the bits between the first bit and the least significant bit among the plurality of bits in the pattern; and adjusting a capacitance of a first capacitor corresponding to the first bit when the number of times that the digital signal equals the pattern exceeds a threshold.
by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values · CPC title
in which the input S/H circuit is merged with the feedback DAC array · CPC title
using switched capacitors · CPC title
over the full range of the converter, e.g. for correcting differential non-linearity · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.