MOS transistor having a gate dielectric with multiple thicknesses

Patent metadata

Field	Value
Publication number	US-9466715-B2
Application number	US-201314015350-A
Country	US
Kind code	B2
Filing date	Aug 30, 2013
Priority date	Aug 30, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.

First claim

What is claimed is:

1. A metal-oxide-semiconductor (MOS) transistor in a semiconductor substrate, comprising:
a well region of a first conductivity type extending into the semiconductor substrate;
a source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type in opposite sides of the well region, wherein the well region has a first portion laterally adjacent to the drain region, a second portion laterally
adjacent to the source region and a third portion laterally between the first portion and the second portion;
a first gate dielectric layer over and overlapped with the first portion of the well region;
a second gate dielectric layer over and overlapped with the first portion and the third portion of the well region, and over the first gate dielectric layer, and in contact with a side surface of the first gate dielectric layer, wherein the side surface of the first gate dielectric layer is adjacent to the drain region;
a third gate dielectric layer over and overlapped with the first portion, the second portion and the third portion of the well region, and over the first gate dielectric layer and the second gate dielectric layer, and in contact with a side surface of the second gate dielectric layer, wherein the side surface of the second gate dielectric layer is adjacent to the drain region; and
a gate electrode over the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer.

2. The MOS transistor of claim 1 , further comprising a first spacer and a second spacer, wherein the first spacer is positioned on a sidewall of the gate electrode and substantially aligned with one edge of the source region, and the second spacer is positioned on another sidewall of the gate electrode and substantially aligned with one edge of the drain region.

3. The MOS transistor of claim 2 , further comprising a first lightly doped drain (LDD) region of the second conductivity type and a second LDD region of the second conductivity type, wherein the first LDD region is positioned beneath the first spacer and adjoining the source region, the second LDD region is positioned beneath the second spacer and adjoining the drain region.

4. The MOS transistor of claim 1 , wherein the source region and the drain region comprise N-type dopants, and the well region comprises P-type dopants.

5. A metal-oxide-semiconductor (MOS) transistor in a semiconductor substrate, comprising:
a first well region of a first conductivity type extending into the semiconductor substrate;
a second well region of a second conductivity type opposite to the first conductivity type extending into the semiconductor substrate and located adjacent to the first well region;
a source region of the second conductivity type and a drain region of the second conductivity type respectively in the first well region and the second well region, wherein the second well region has a first portion laterally adjacent to the drain region, a second portion laterally adjacent to the first well region and a third portion laterally between the first portion and the second portion;
a first gate dielectric layer over and overlapped with the first portion of the second well region;
a second gate dielectric layer over and overlapped with the first portion and the third portion of the second well region, and over the first gate dielectric layer, and in contact with a side surface of the first gate dielectric layer, wherein the side surface of the first gate dielectric layer is adjacent to the drain region;
a third gate dielectric layer over and overlapped with the first portion, the second portion and the third portion of the second well region and the first well region, and over the first gate dielectric layer and the second gate dielectric layer, and in contact with a side surface of the second gate dielectric layer, wherein the side surface of the second gate dielectric layer is adjacent to the drain region; and
a gate electrode over the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer.

6. The MOS transistor of claim 5 , wherein a distance that the gate electrode overlaps with the first well region is less than a distance that the gate electrode overlaps with the second well region.

7. The MOS transistor of claim 5 , further comprising a first spacer and a second spacer, the first spacer on a sidewall of the gate electrode and substantially aligned with one edge of the source region, the second spacer on another sidewall of the gate electrode and substantially aligned with one edge of the drain region.

8. The MOS transistor of claim 7 , further comprising a first lightly doped drain (LDD) region of the second conductivity type and a second LDD region of the second conductivity type, the first LDD region beneath the first spacer and adjoining the source region, the second LDD region beneath the second spacer and adjoining the drain region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chih-Chang
• Chu Fu-Yu
• Liu Ruey-Hsin

Classifications

• H10P14/6326

  Deposition processes · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title