Interconnect structure for an integrated circuit and method of fabricating an interconnect structure

Patent metadata

Field	Value
Publication number	US-9466563-B2
Application number	US-201414557111-A
Country	US
Kind code	B2
Filing date	Dec 1, 2014
Priority date	Dec 1, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first metallization level including a first metal routing path; and
a second metallization level overlying the first metallization level, said second metallization level including:
a dielectric layer;
a via opening formed in said dielectric layer extending vertically through the dielectric layer to a top surface of the first metal routing path, wherein the via opening has a self-aligned direction and a non-self-aligned direction;
a metal plug at a bottom of the via opening in direct contact with the first metal routing path which leaves a remaining opening in the via opening, wherein a width of the metal plug in the self-aligned direction is less than a width of the metal plug in the non-self-aligned direction; and
a metal material which fills the remaining opening to define a second metal routing path;
wherein the metal plug is formed of cobalt or an alloy including cobalt.

2. The circuit of claim 1 , wherein the metal plug extends to a maximum height which is less than a height of the dielectric layer through which the via opening extends.

3. The circuit of claim 1 , wherein the metal material comprises a conformal liner and a metal fill.

4. The circuit of claim 2 , wherein the maximum height of the metal plug is between one-third and one-half of the height of the dielectric layer.

5. The circuit of claim 2 , wherein the maximum height is between 10 nm and 30 nm, where a width of the metal plug is between 15 nm and 40 nm.

6. The circuit of claim 5 , wherein the width of the metal plug is between 15 nm and 22 nm in the self-aligned direction and between 22 nm and 40 nm in the non-self-aligned direction.

7. The circuit of claim 3 , wherein the metal fill comprises copper.

8. The circuit of claim 3 , wherein the conformal liner provides a barrier layer.

9. The circuit of claim 3 , wherein the conformal liner provides a seed layer.

10. A circuit, comprising:
a metallization level which includes a first metal routing path;
a dielectric layer over said metallization level, the dielectric layer including a via opening extending vertically completely through the dielectric layer and aligned with a top surface of the first metal routing path, said via opening having a width and a first height and further having a self-aligned direction and a non-self-aligned direction;
a metal plug that is not a conformal liner disposed at a bottom of the via opening in direct contact with the top surface of the first metal routing path, said metal plug having a second height less than the first height, wherein a width of the metal plug in the self-aligned direction is less than a width of the metal plug in the non-self-aligned direction;
wherein the metal plug is formed of cobalt or an alloy including cobalt; and
a second metal routing path disposed within the via opening in contact with the metal plug;
wherein the second metal routing path is made of a material different than the metal plug.

11. The circuit of claim 10 , wherein the second metal routing path comprises:
a conformal liner in contact with the metal plug; and
a metal fill over the conformal liner.

12. The circuit of claim 11 , wherein the metal fill comprises copper.

13. The circuit of claim 11 , wherein the conformal liner is a barrier layer.

14. The circuit of claim 11 , wherein the conformal liner is a seed layer.

15. A circuit, comprising:
a metallization level which includes a first metal routing path;
an adhesion layer on said metallization level;
a dielectric layer on said adhesion layer;
a via opening extending vertically completely through the dielectric layer and the adhesion layer to a top surface of the first metal routing path, wherein the via opening has a self-aligned direction and a non-self-aligned direction;
a metal plug disposed at a bottom of the via opening in direct contact with the top surface of the first metal routing path, said metal plug having a height across its width that is greater than a thickness of the adhesion layer but less than a combined thickness of the adhesion layer and dielectric layer, wherein a width of the metal plug in the self-aligned direction is less than a width of the metal plug in the non-self-aligned direction;
wherein the metal plug is formed of cobalt or an alloy including cobalt; and
a second metal routing path disposed within the via opening in contact with the metal plug;
wherein the second metal routing path is made of a material different than the metal plug.

16. The circuit of claim 15 , wherein the thickness of the adhesion layer is 10-30 nm and a thickness of the dielectric layer greater than the thickness of the adhesion layer.

17. The circuit of claim 16 , wherein the thickness of the dielectric layer is 30-1000 nm.

18. The circuit of claim 16 , wherein the thickness of the dielectric layer is 60-200 nm.

Assignees

• St Microelectronics Inc
• IBM

Inventors

• Mignot Yann
• Spooner Terry
• Kelly James John

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/46

  using a liquid · CPC title