Semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-9252129-B2
Application number	US-201213602257-A
Country	US
Kind code	B2
Filing date	Sep 3, 2012
Priority date	Mar 13, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

First claim

What is claimed is:

1. A semiconductor apparatus comprising:
a slave chip comprising a signal transfer unit configured to determine whether to transfer an input signal in response to a chip select signal;
a master chip comprising a replica circuit unit having a similar configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to a control signal by selecting one of the output signal of the signal transfer unit and the output signal of the replica circuit unit;
a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and
a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

2. The semiconductor apparatus according to claim 1 , wherein the signal output unit outputs a signal outputted from the signal transfer unit as the output signal when the control signal is activated, and outputs a signal outputted from the replica circuit unit as the output signal when the control signal is deactivated.

3. The semiconductor apparatus according to claim 1 , wherein the replica circuit unit determines whether to transfer the input signal in response to the control signal.

4. The semiconductor apparatus according to claim 3 , wherein the replica circuit unit transfers the input signal to the signal output unit when the control signal is deactivated.

5. The semiconductor apparatus according to claim 1 , wherein the input signal comprises a pulse signal having a predetermined cycle.

6. The semiconductor apparatus according to claim 1 , wherein the chip select signal is activated when the slave chip is stacked at the uppermost layer among a plurality of stacked semiconductor chips.

7. The semiconductor apparatus according to claim 1 , wherein the chip select signal is activated when the slave chip is stacked at the uppermost layer among a plurality of stacked semiconductor chips.

8. A semiconductor apparatus comprising:
a slave chip comprising having a signal transfer unit configured to determine whether to transfer an input signal in response to a chip select signal;
a master chip comprising a replica circuit unit having a similar configuration as the signal transfer unit, a signal path selection unit configured to transmit the input signal to the signal transfer unit or the replica circuit unit in response to a control signal, and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and output an output signal in response to the control signal;
a first through-chip via vertically formed through the slave chip, and having one end connected to the signal path selection unit and the other end connected to the signal transfer unit; and
a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and is the other end connected to the signal output unit.

9. The semiconductor apparatus according to claim 8 , wherein the signal path selection unit transmits the input signal to the signal transfer unit when the control signal is activated, and transmits the input signal to the replica circuit unit when the control signal is deactivated.

10. The semiconductor apparatus according to claim 8 , wherein the signal output unit outputs a signal outputted from the signal transfer unit as the output signal when the control signal is activated, and outputs a signal outputted from the replica circuit unit as the output signal when the control signal is deactivated.

11. The semiconductor apparatus according to claim 8 , wherein the replica circuit unit determines whether to transmit the input signal in response to the control signal.

12. The semiconductor apparatus according to claim 11 , wherein the replica circuit unit transmits the input signal to the signal output unit when the control signal is deactivated.

13. The semiconductor apparatus according to claim 8 , wherein the control signal comprises a test mode signal.

14. The semiconductor apparatus according to claim 8 , wherein the input signal comprises a pulse signal having a predetermined cycle.

15. The semiconductor apparatus according to claim 8 , wherein the chip select signal is activated when the slave chip is stacked at the uppermost layer among a plurality of stacked semiconductor chips.

Assignees

• Yun Tae Sik
• Byeon Sang Jin
• Sk Hynix Inc

Inventors

• Yun Tae Sik
• Byeon Sang Jin

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/00 Primary

  Package configurations · CPC title