Path isolation in a memory device

Patent metadata

Field	Value
Publication number	US-9466365-B2
Application number	US-201615018585-A
Country	US
Kind code	B2
Filing date	Feb 8, 2016
Priority date	Sep 9, 2011
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a memory cell of a memory device;
a bit-line electrode coupled with a single transistor bit-line coupled with the memory cell;
a word-line electrode coupled with a single transistor word-line coupled with the memory cell, a capacitance of the word-line electrode is lower than a capacitance of the bit-line electrode, and a potential of the word-line electrode is lower than a potential of the bit-line electrode; and
write circuitry coupled with the word-line electrode, the write circuitry to perform a write operation of the memory cell.

2. The apparatus of claim 1 , further comprising:
current-limiting circuitry of a selection module coupled with the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, the current-limiting circuitry includes a current-mirror circuit.

3. The apparatus of claim 2 , further comprising:
sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of the memory cell via a comparison of a first voltage generated responsive to a first load on the single transistor word-line to a second voltage generated by a second load to a reference current, the first load equivalent to the second load.

4. The apparatus of claim 1 , wherein the memory cell is a memory cell of a three-dimensional array of memory cells, the single transistor word-line is a first single transistor word-line extending in a first dimension of the three-dimensional array, the single transistor bit-line extends in a second dimension of the three-dimensional array, and the memory cell is a first memory cell, the apparatus further comprising:
a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and
a second single transistor word-line coupled to with the word-line electrode and further coupled with the second memory cell, wherein the single transistor bit-line extends between the first single transistor word-line and the second single transistor word-line.

5. The apparatus of claim 1 , comprising:
the memory cell, the single transistor bit-line, and the single transistor word-line are part of a tile including a plurality of memory cells, single transistor bit-lines, and single transistor word-lines;
the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor bit-line;
the tile has a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor word-line;
the first linear dimension is greater than the second linear dimension; and
the tile includes a ratio of two single transistor word-lines for each single transistor bit-line.

6. The apparatus of claim 1 , wherein the write circuitry comprises a current profile generator to generate a current profile for a set or reset operation of the memory cell, the set current profile including a stepped or ramp shaped current profile, the reset current profile including a rectangle current profile.

7. The apparatus of claim 1 , the memory device is a phase change memory and switch (PCMS) device.

8. The apparatus of claim 7 , the PCMS device includes chalcogenide glass.

9. An apparatus comprising:
a first memory cell of a three-dimensional array of memory cells;
a single transistor bit-line coupled to the first memory cell, the single transistor bit-line extends in a first dimension of the three-dimensional array;
a first single transistor word-line coupled to the first memory cell, the first single transistor word-line extends in a second dimension of the three-dimensional array;
a bit-line electrode coupled to the single transistor bit-line;
a word-line electrode coupled to the first single transistor word-line, a potential of the word-line electrode is lower than a potential of the bit-line electrode; and
current-limiting circuitry of a selection module coupled to the word-line electrode, the current-limiting circuitry to facilitate a selection operation of the first memory cell by the selection module.

10. The apparatus of claim 9 , further comprising:
a second memory cell of the three-dimensional array of memory cells, the second memory cell being in a stacked configuration with the first memory cell in a third dimension of the three-dimensional array; and
a second single transistor word-line coupled to the word-line electrode and further coupled to the second memory cell, wherein the single transistor bit-line extends between the first single transistor word-line and the second single transistor word-line.

11. The apparatus of claim 9 , the current-limiting circuitry comprises a current-mirror circuit.

12. The apparatus of claim 9 , further comprising:
sensing circuitry coupled to the word-line electrode, the sensing circuitry to perform a read operation of the first and second memory cells via a comparison of respective first voltages generated responsive to a first load on the respective first and second single transistor word-lines to a second voltage generated by a second load to a reference current, the first load equivalent to the second load.

13. The apparatus of claim 9 , further comprising:
write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the first and second memory cells.

14. The apparatus of claim 13 , wherein the write circuitry comprises a current profile generator to generate a current profile for a set or reset operation of the first or second memory cells, the set current profile including a stepped or ramp shaped current profile, the reset current profile including a rectangle current profile.

15. The apparatus of claim 9 , the first and second memory cells comprising phase change memory that includes chalcogenide glass.

16. An apparatus comprising:
a memory cell of a memory device;
a single transistor bit-line coupled with the memory cell;
a single transistor word-line coupled with the memory cell;
a bit-line electrode coupled with the bit-line;
a word-line electrode coupled with the single transistor word-line, a potential of the word-line electrode is lower than a potential of the bit-line electrode; and
sensing circuitry coupled with the word-line electrode, the sensing circuitry to perform a read operation of the memory cell via a comparison of a first voltage generated responsive to a first load on the single transistor word-line to a second voltage generated by a second load to a reference current, the first load equivalent to the second load, wherein:
the memory cell, the single transistor bit-line, and the single transistor word-line are part of a tile including a plurality of memory cells, single transistor bit-lines, and single transistor word-lines, the tile has a first linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor bit-line;
the tile has a second linear dimension that extends in a direction that is parallel to a lengthwise dimension of the single transistor word-line;
the first linear dimension is greater than the second linear dimension; and
the tile includes a higher number of word-lines compared to bit-lines.

17. The apparatus of claim 16 , further comprising:
current-limiting circuitry of a selection module coupled with the word-line electrode, the current-limiting circuitry to facilitate a selection opera

Assignees

• Intel Corp
• Intel Corp

Inventors

• Castro Hernan A

Classifications

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C13/02

  using elements whose operation depends upon chemical change {(G11C13/0009 takes precedence)} · CPC title