Bridge circuitry for communications with dynamically reconfigurable circuits

Patent metadata

Field	Value
Publication number	US-9465763-B2
Application number	US-201313919899-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jun 17, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented.

First claim

What is claimed is:

1. Circuitry, comprising:
first and second communications interfaces, wherein communications requirements of the second communications interface vary based on changes to a communication protocol of the second communications interface from a first protocol to a second protocol;
interface circuitry coupled between the first and second interfaces, wherein the interface circuitry has a first mode for processing communications of the first protocol and a second mode for processing communications of the second protocol; and
control circuitry that controls the interface circuitry to switch between the first and second modes based on the variable communications requirements of the second interface without interrupting communications at the first interface while the first communications interface processes communications.

2. The circuitry defined in claim 1 wherein the first interface receives transactions and wherein the interface circuitry comprises a buffer that stores the received transactions.

3. The circuitry defined in claim 2 wherein the interface circuitry further comprises interface conversion circuitry that transmits information retrieved from the stored transactions from the second interface based on the variable communications requirements of the second interface.

4. The circuitry defined in claim 3 wherein the transactions are received at the first interface using a first protocol, wherein the variable communications requirements of the second interface identify a second protocol, and wherein the interface conversion circuitry comprises interface type conversion circuitry that transmits the information from the stored transactions from the second interface using the second protocol.

5. The circuitry defined in claim 4 wherein the first and second interfaces have respective first and second widths, wherein the transactions are associated with the first width, and wherein the interface conversion circuitry further comprises width conversion circuitry that converts the information from the stored transactions to the second width.

6. The circuitry defined in claim 5 wherein the transactions received at the first interface include addresses corresponding to a first address space, wherein the second interface is associated with a second address space, and wherein the interface conversion circuitry further comprises address remapping circuitry that maps the addresses of the first address space to the second address space.

7. The circuitry defined in claim 3 wherein the information transmitted at the second interface includes signals, wherein the variable communications requirements of the second interface include timing requirements, and wherein the interface circuitry further comprises timing circuitry that controls timing of the transmitted signals to satisfy the timing requirements.

8. The circuitry defined in claim 7 wherein the timing circuitry includes latency compensation circuitry that delays at least a portion of the transmitted signals to satisfy the timing requirements.

9. The circuitry defined in claim 7 wherein the first interface is associated with a first clock domain, wherein the second interface is associated with a second clock domain, and wherein the timing circuitry includes clock crossing circuitry that interfaces between the first and second clock domains.

10. The circuitry defined in claim 2 wherein the variable communications requirements include priority assignment information, wherein interface circuitry processes the stored transactions in the buffer in an order, and wherein the interface circuitry further comprises priority sorting circuitry that determines the order in which the stored transactions are processed based on the priority assignment information.

11. The circuitry defined in claim 1 wherein the first interface is coupled to dedicated circuitry that provides the transactions and wherein the second interface is coupled to dynamically reconfigurable circuitry that provides the variable communications requirements of the second interface.

12. A method of operating a bridge circuit having first and second interfaces that are coupled to respective circuitry, the method comprising:
with interface circuitry, receiving communications at the first interface;
with the interface circuitry, transmitting the received communications at the second interface using communications settings, wherein the communications settings comprise a communications protocol; and
while processing the communications at the first interface, using control circuitry to adjust the communications protocol used by the interface circuitry to transmit the received communications at the second interface without interrupting the communications at the first interface.

13. The method defined in claim 12 further comprising:
with storage circuitry, buffering the communications received at the first interface.

14. The method defined in claim 13 wherein the circuitry coupled to the second interface comprises dynamically reconfigurable circuitry, the method further comprising:
detecting a reconfiguration request for the dynamically reconfigurable circuitry coupled to the second interface, wherein buffering the communications received at the first interface comprises buffering the communications received at the first interface while the dynamically reconfigurable circuitry is being reconfigured.

15. The method defined in claim 13 further comprising:
with the control circuitry, receiving an interface request at the second interface; and
with the control circuitry, identifying interface parameters from the interface request, wherein adjusting the communications settings of the second interface without interrupting the communications at the first interface comprises adjusting the communications settings of the second interface based on the identified interface parameters.

16. The method defined in claim 15 wherein identifying the interface parameters from the interface request comprises identifying at least one interface parameter selected from the group consisting of: bus width parameters, bandwidth parameters, timing requirement parameters, clock parameters, address map parameters, and priority assignment parameters.

17. The method defined in claim 13 further comprising:
detecting an emergency reconfiguration event; and
in response to detecting the emergency reconfiguration event, temporarily terminating the communications at the first interface.

18. Apparatus, comprising:
circuitry;
dynamically reconfigurable circuitry that is reconfigurable between at least first and second configurations during normal operation of the circuitry, wherein the dynamically reconfigurable circuitry uses at least first and second communications protocols that are respectively associated to the at least first and second configurations during normal operation of the circuitry; and
a bridge circuit having a first interface coupled to the circuitry and a second interface coupled to the dynamically reconfigurable circuitry, wherein the bridge circuit interfaces between the circuitry and the first and second configurations of the dynamically reconfigurable circuitry without interrupting the circuitry, wherein the bridge circuit has a first mode associated with the first communications protocol and a second mode for associated with the second communications protocol, wherein the bridge circuit switches between the first and second modes based on the configurations of the dynamically reconfigurable circuitry.

19. The apparatus defined in

Assignees

• Altera Corp

Inventors

• Pelt Robert L
• Hedinger Sam

Classifications

• G06F13/4054

  where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus · CPC title

• G06F13/4018

  with data-width conversion · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title