Electric connection element manufacturing method

Patent metadata

Field	Value
Publication number	US-9460960-B2
Application number	US-201514838976-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Sep 2, 2014
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process of performing at least one step of dipping the substrate into a manganese amidinate solution. A copper layer is then deposited on the manganese silicate layer using a process of performing a step of dipping the substrate into a copper amidinate solution. An anneal is performed to stabilize one or both of the manganese silicate layer and copper layer.

First claim

The invention claimed is:

1. A method of manufacturing an electric connection element on a surface of a silicon substrate coated with a silicon oxide layer, comprising the steps of:
a) depositing a manganese silicate layer on the silicon oxide layer by performing at least one step of dipping the substrate into a manganese amidinate solution; and
b) depositing a copper layer above the manganese silicate layer by performing at least one step of dipping the substrate into a copper amidinate solution.

2. The method of claim 1 , wherein step a) comprises a plurality of successive steps of dipping the substrate into the manganese amidinate solution, alternating with steps of applying a plasma containing oxygen.

3. The method of claim 1 , further comprising performing an anneal after the deposition of the copper layer.

4. The method of claim 3 , wherein said anneal is carried out at a temperature in the range from 200 to 350° C. for approximately 1 hour under an atmosphere containing a mixture of argon and of dihydrogen.

5. The method of claim 2 , further comprising performing an intermediate anneal between step a) and step b).

6. The method of claim 5 , wherein said intermediate anneal is carried out at a temperature in the range from 200 to 350° C. for approximately 1 hour under a neutral atmosphere, for example, under pure argon.

7. The method of claim 1 , wherein, at step a), said at least one dipping step is carried out at ambient temperature, under an atmosphere containing a neutral gas such as argon.

8. The method of claim 1 , wherein, at step b), the dipping step is carried out at a temperature in the range from 80 to 150° C., under an atmosphere containing dihydrogen, for a duration in the range from 1 to 3 hours.

9. The method of claim 1 , wherein the manganese amidinate solution and the copper amidinate solution each comprise a solvent selected from the group consisting of anisole and toluene.

10. The method of claim 1 , wherein said surface is the surface of a via crossing all or part of the thickness of the substrate.

11. A method, comprising:
forming an opening in a surface of a semiconductor substrate;
coated surfaces of the opening with a silicon oxide layer;
depositing a manganese silicate layer on the silicon oxide layer, said manganese silicate layer derived from a manganese amidinate solution applied to the silicon oxide layer; and
depositing a copper layer on the manganese silicate layer.

12. The method of claim 11 , wherein the copper layer is derived from a copper amidinate solution applied to the manganese silicate layer.

13. The method of claim 11 , wherein depositing the manganese silicate layer comprises successively dipping the substrate into the manganese amidinate solution in an alternating manner with applying a plasma containing oxygen.

14. The method of claim 11 , further comprising performing an anneal after depositing the copper layer.

15. The method of claim 11 , further comprising performing an anneal between depositing the manganese silicate layer and depositing the copper layer.

16. The method of claim 11 , wherein the manganese amidinate solution comprises a solvent selected from the group consisting of anisole and toluene.

17. The method of claim 11 , wherein said opening is associated with a crossing all or part of the thickness of the substrate.

18. A method of manufacturing an electric connection element on a silicon oxide layer supported by a substrate, comprising the steps of:
a) dipping the substrate into a manganese amidinate solution to form a manganese silicate layer on the silicon oxide layer; and
b) dipping the substrate into a copper amidinate solution to form a copper layer above the manganese silicate layer.

19. The method of claim 18 , wherein step a) further comprises applying a plasma containing oxygen after dipping the substrate into the manganese amidinate solution.

20. The method of claim 18 , further comprising performing an anneal after the step b).

21. The method of claim 18 , further comprising performing an anneal between step a) and step b).

22. The method of claim 18 , wherein the manganese amidinate solution and the copper amidinate solution each comprise a solvent selected from the group consisting of anisole and toluene.

23. The method of claim 18 , further comprising forming a via crossing all or part of a thickness of the substrate, lining a surface of the via with the silicon oxide layer, and then performing steps a) and b).

Assignees

• St Microelectronics Tours Sas
• Centre Nat De La Rech Scientifique—Cnrs
• Centre Nat De La Rech Scientifique-Cnrs

Inventors

• Piettre Kilian
• Fau Pierre
• Cure Jeremy
• Chaudret Bruno

Classifications

• H10P14/46

  using a liquid · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/052

  by treatments not introducing additional elements therein · CPC title

• H10W20/043

  for electroplating · CPC title