Memory system

Patent metadata

Field	Value
Publication number	US-9460813-B2
Application number	US-201313933812-A
Country	US
Kind code	B2
Filing date	Jul 2, 2013
Priority date	Mar 14, 2013
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

According to one embodiment, there is provided a memory system that is connected to a host apparatus. The memory system includes a transmitting port and a controller. The transmitting port transmits a transmission signal to the host apparatus. The controller includes a first output interface that is connected to the transmitting port and a second output interface that is connected to the transmitting port. The memory system is configured such that a drivability of an output from the first output interface is larger than a drivability of an output from the second output interface in a first mode.

First claim

What is claimed is:

1. A memory system comprising:
a first transmitting port connectable to a first host apparatus; and
a controller that is configured to transmit a transmission signal to the first host apparatus through the first transmitting port, that includes a first output interface and a second output interface, that outputs a first signal from the first output interface to the first transmitting port, and that outputs a second signal from the second output interface to the first transmitting port, the first signal being
selected from a plurality of first signals, the plurality of first signals including high impedance, the second signal being selected from a plurality of second signals, the plurality of second signals not including high impedance; and
a signal line including a first signal line, a second signal line and a third signal line, the first signal line being connected to the first transmitting port, the second signal line being diverged from the first signal line, the second signal line being connected to the first output interface through a first resistor, the third signal line being diverged from the first signal line, the third signal line being connected to the second output interface through a second resistor, the second resistor having a greater resistance value than the first resistor.

2. The memory system according to claim 1 ,
wherein the controller supplies the first signal output from the first output interface as the transmission signal to the first transmitting port in a first mode, and supplies the second signal output from the second output interface as the transmission signal to the first transmitting port in a second mode.

3. The memory system according to claim 2 ,
wherein the second resistor has a greater resistance value than the first resistor such that the first signal output from the first output interface can be supplied to the first transmitting port when the second signal with a fixed level is output from the second output interface in the first mode.

4. The memory system according to claim 2 ,
wherein the plurality of first signals include a first voltage, a second voltage lower than the first voltage, and the high impedance,
the plurality of second signals include a third voltage and a fourth voltage lower than the third voltage,
in the first mode, the controller outputs the first voltage and/or the second voltage from the first output interface and steadily outputs the third voltage or the fourth voltage from the second output interface, and
in the second mode, the controller outputs the high impedance from the first output interface and outputs the third voltage and/or the fourth voltage from the second output interface.

5. The memory system according to claim 4 ,
wherein the second resistor has a greater resistance value than the first resistor such that the first voltage and/or the second voltage output from the first output interface can be supplied to the first transmitting port when the third voltage or the fourth voltage is steadily output from the second output interface in the first mode.

6. The memory system according to claim 4 ,
wherein the first output interface includes a first PMOS transistor and a first NMOS transistor,
the second output interface includes a second PMOS transistor and a second NMOS transistor,
the first output interface outputs the first voltage when the first PMOS transistor is turned on and the first NMOS transistor is turned off, outputs the second voltage when the first PMOS transistor is turned off and the first NMOS transistor is turned on, and outputs the high impedance when the first PMOS transistor is turned off and the first NMOS transistor is turned off, and
the second output interface outputs the third voltage when the second PMOS transistor is turned on and the second NMOS transistor is turned off, and outputs the fourth voltage when the second PMOS transistor is turned off and the second NMOS transistor is turned on.

7. The memory system according to claim 6 ,
wherein the controller includes:
a first selector that selects one of a first transmission control signal and a signal fixed to the high level and supplies the selected signal to a gate of the first PMOS transistor, in response to a first control signal; and
a second selector that selects one of the first transmission control signal to be transmitted and a signal fixed to a low level and supplies the selected signal to a gate of the first NMOS transistor, in response to the first control signal.

8. The memory system according to claim 1 ,
wherein the controller further includes a third output interface,
the signal line further includes a fourth signal line diverged from the first signal line,
the fourth signal line is connected to the third output interface through a third resistor,
the second resistor has a greater resistance value than the third resistor, and
the controller outputs a third signal from the third output interface, the third signal being selected from the plurality of third signals, the plurality of third signals including high impedance.

9. A memory system comprising:
a first transmitting port connectable to a first host apparatus; and
a controller that is configured to transmit a transmission signal to the first host apparatus through the first transmitting port, that includes a first output interface and a second output interface, that outputs a first signal from the first output interface to the first transmitting port, and that outputs a second signal from the second output interface to the first transmitting port, the first signal being selected from a plurality of first signals, the plurality of first signals including high impedance, the second signal being selected from a plurality of second signals, the plurality of second signals not including high impedance,
wherein the first output interface includes a first PMOS transistor and a first NMOS transistor,
the second output interface includes a second PMOS transistor and a second NMOS transistor, and
the memory system satisfies at least either one of a condition that a dimension of the second NMOS transistor is less than a dimension of the first NMOS transistor and a condition that a dimension of the second PMOS transistor is less than a dimension of the first PMOS transistor.

10. The memory system according to claim 9 ,
wherein the memory system satisfies at least either one of the condition that the dimension of the second NMOS transistor is less than the dimension of the first NMOS transistor and the condition that the dimension of the second PMOS transistor is less than the dimension of the first PMOS transistor, such that the first signal output from the first output interface can be supplied to the transmitting port when the fixed-level second signal is output from the second output interface in the first mode.

11. The memory system according to claim 10 ,
wherein the first output interface outputs a first voltage when the first PMOS transistor is turned on and the first NMOS transistor is turned off, outputs a second voltage when the first PMOS transistor is turned off and the first NMOS transistor is turned on, and outputs the high impedance when the first PMOS transistor is turned off and the first NMOS transistor is turned off, and
the second output interface outputs a third voltage when the second PMOS transistor is turned on and the second NMOS transistor is turned off, and outputs a fourth voltage when the second PMOS transistor is turned off and the second NMOS transistor is turned on.

12. The memory system according to claim 1 ,
wherein the controller makes an operation mode transition to a first mo

Assignees

• Toshiba Kk

Inventors

• Hashimoto Daisuke
• Eguchi Toyokazu
• Matsumoto Hajime
• Ide Daisuke

Classifications

• G06F2213/0026

  PCI express · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title

• G06F2213/0032

  Serial ATA [SATA] · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• G11C29/46 Primary

  Test trigger logic · CPC title