Pin removal mode signal generation circuit and semiconductor apparatus including the same

Patent metadata

Field	Value
Publication number	US-9239354-B2
Application number	US-201213708147-A
Country	US
Kind code	B2
Filing date	Dec 7, 2012
Priority date	Jun 28, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A pin removal mode signal generation circuit includes: a set signal generation unit configured to activate a set signal when an activated test mode signal pulse is generated by a mode register set and an activated flag signal pulse is applied, and a pin removal mode signal generation unit configured to activate a pin removal mode signal when the set signal is activated, and deactivate the pin removal mode signal when a reset signal is activated.

First claim

What is claimed is:

1. A pin removal mode signal generation circuit included in a semiconductor device, comprising:
a set signal generation unit configured to activate a set signal when a test mode signal is activated and a flag signal is activated; and
a pin removal mode signal generation unit configured to receive the set signal and a reset signal, activate a pin removal mode signal when the set signal is activated, and deactivate the pin removal mode signal when the reset signal is activated,
wherein the reset signal is generated when the semiconductor device is reset.

2. The pin removal mode signal generation circuit according to claim 1 , further comprising an external clock enable signal input pin receiving a clock enable signal,
wherein when the clock enable signal is activated to a low level, the clock enable signal becomes the flag signal, and
wherein the set signal generation unit generates the set signal having the active state when the clock enable signal becomes the flag signal.

3. The pin removal mode signal generation circuit according to claim 2 , wherein the flag signal is activated to a low level when the clock enable signal is activated to a high level.

4. The pin removal mode signal generation circuit according to claim 3 , wherein the set signal generation unit comprises a NAND gate configured to receive the test mode signal and a signal obtained by inverting the flag signal and output the set signal.

5. The pin removal mode signal generation circuit according to claim 4 , wherein the pin removal mode signal generation unit comprises a latch configured to receive the set signal and the reset signal.

6. The pin removal mode signal generation circuit according to claim 1 , further comprising a normal test mode signal generation unit configured to generate an activated normal test mode signal when the test mode signal is activated and the flag signal is deactivated.

7. A semiconductor apparatus comprising:
a pin removal mode signal generation circuit configured to activate a pin removal mode signal when an activated test mode signal pulse is generated by a mode register set and an activated flag signal pulse is applied; and
a pin removal mode test circuit configured to latch a test address by receiving addresses through overall address pins during a normal test mode when the activated pin removal mode signal is not applied, and to latch the test address by sequentially receiving the addresses through a part of the address pins when the activated pin removal mode signal is applied.

8. The semiconductor apparatus according to claim 7 , wherein the pin removal mode signal generation circuit further comprises an external clock enable signal input pin receiving a clock enable signal and the flag signal pulse is applied through the external clock enable signal input pin, and
wherein the external clock enable signal input pin is configured to receive the clock enable signal when the pin removal mode signal is not activated and to receive the flag signal pulse when the pin removal mode signal is activated.

9. The semiconductor apparatus according to claim 8 , wherein the flag signal pulse is activated to a low level when the clock enable signal is activated to a high level.

10. The semiconductor apparatus according to claim 7 , wherein the pin removal mode signal generation circuit comprises:
a set signal generation unit configured to activate a set signal when the activated test mode signal pulse is generated and the activated flag signal pulse is applied; and
a pin removal mode signal generation unit configured to receive the set signal and a reset signal, activate the pin removal mode signal when the set signal is activated, and deactivate the pin removal mode signal when the reset signal is activated,
wherein the reset signal is generated when a semiconductor apparatus is reset.

11. The semiconductor apparatus according to claim 7 , wherein the pin removal mode test circuit comprises:
a pin removal mode address latch section configured to latch a former-entry address received through a first address input pin in synchronization with an inverted clock signal and output the latched signal as a first pin removal address, when the activated pin removal mode signal is applied;
a first address latch section configured to latch the first pin removal address as a first test address in synchronization with a clock signal when the activated pin removal mode signal is applied; and
a second address latch section configured to latch a latter-entry address received through the second address input pin as a second test address in synchronization with the clock signal.

12. The semiconductor apparatus according to claim 11 , wherein a phase of the first pin removal address leads a phase of the first test address by a half clock, and the phase of the first test address and a phase of the second test address are identical to each other.

13. The semiconductor apparatus according to claim 11 , wherein the first address latch section latches an address received through a first address input pin as the first test address in synchronization with the clock signal during the normal test mode.

14. A semiconductor apparatus comprising:
a pin removal mode test circuit configured to latch a test address by receiving addresses through overall address pins during a normal test mode, and latch the test address by sequentially receiving the addresses through a part of the address pins during a pin removal mode; and
a pin removal mode signal generation circuit configured to control the pin removal mode test circuit of entering the pin removal mode when an activated test mode signal pulse is generated by a mode register set and an activated flag signal pulse is applied, and control the pin removal mode test circuit of entering the normal test mode when a deactivated flag signal is applied.

15. The semiconductor apparatus according to claim 14 , wherein the pin removal mode signal generation circuit further comprises an external clock enable signal input pin receiving a clock enable signal and the flag signal pulse is applied through the external clock enable signal input pin, and
wherein the external clock enable signal input pin is configured to receive the clock enable signal during the normal test mode and to receive the flag signal pulse during the pin removal mode.

16. The semiconductor apparatus according to claim 15 , wherein the flag signal pulse is activated to a low level when the clock enable signal is activated to a high level.

17. The semiconductor apparatus according to claim 14 , wherein the pin removal mode signal generation circuit comprises:
a set signal generation unit configured to activate a set signal when the activated test mode signal pulse is generated and the activated flag signal pulse is applied;
a normal test mode signal generation unit configured to generate an activated normal test mode signal when the activated test mode signal pulse is generated and the set signal is deactivated; and
a pin removal mode signal generation unit configured to receive the set signal and a reset signal, activate a pin removal mode signal when the set signal is activated, and deactivate the pin removal mode signal when the reset signal is activated,
wherein the reset signal is generated when a semiconductor apparatus is reset.

18. The semiconductor apparatus according to claim 14 , wherein the pin removal mode test circuit comprises:
a pin removal mode address latch section configured to latch a former-entry address received through a second addre

Assignees

• Sk Hynix Inc

Inventors

• Lee Yong Woo

Classifications

• G11C29/46

  Test trigger logic · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C29/48

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title

• G01R31/2607 Primary

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G11C29/00

  Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation · CPC title