Signal processing apparatus, signal processing method, program, and signal transmission system

Patent metadata

Field	Value
Publication number	US-9456232-B2
Application number	US-201414477375-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Oct 8, 2013
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Provided is a signal processing apparatus, including: a mapping unit configured to map one of an 8K video signal and a 4K video signal into SDI data streams on a plurality of channels, the SDI data streams on the plurality of channels each conforming to a predetermined Serial Digital Interface (SDI) format; and multiplexing units configured to perform one of 8B/10B conversion and scrambling of the SDI data streams on the plurality of channels in units of a predetermined bit, and multiplex the SDI data streams on the plurality of channels subjected to the one of the 8B/10B conversion and the scrambling, to thereby generate serial data streams in a plurality of lanes, the serial data streams in the plurality of lanes each having a bit rate within a range of from 25 Gbps to 28.3 Gbps.

First claim

What is claimed is:

1. A signal processing apparatus, comprising:
circuitry configured to:
map one of an 8K video signal and a 4K video signal into Serial Digital Interface (SDI) data streams on a plurality of channels, the SDI data streams on the plurality of channels each conforming to a predetermined SDI format;
perform one of 8B/10B conversion and scrambling of the SDI data streams on the plurality of channels in units of a predetermined bit, and multiplex the SDI data streams on the plurality of channels subjected to the one of the 8B/10B conversion and the scrambling, to thereby generate serial data streams in a plurality of lanes, the serial data streams in the plurality of lanes each having a bit rate within a range of from 25 Gbps to 28.3 Gbps; and
secure an area for multiplexing ancillary data containing audio data within a horizontal ancillary data area of each of the SDI data streams on the plurality of channels.

2. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to:
an 8K video signal of 48P-60P/4:4:4/10 bits,
an 8K video signal of 48P-60P/4:4:4/12 bits, and
an 8K video signal of 48P-60P/4:2:2/12 bits into one of
first SDI data streams on 64 channels, the first SDI data streams on the 64 channels each conforming to an HD-SDI format, and
second SDI data streams on 32 channels, the second SDI data streams on the 32 channels each conforming to a 3G-SDI format,

perform the 8B/10B conversion in units of 40 bits of the one of
the first SDI data streams on any one of odd-numbered channels and even-numbered channels of the 64 channels, and
the second SDI data streams on any one of odd-numbered channels and even-numbered channels of the 32 channels,

extract 32-bit data items from each of the units of 40 bits of the one of
the first SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 64 channels, and
the second SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 32 channels,

perform the 8B/10B conversion of the extracted 32-bit data items, and
multiplex the one of
the first SDI data streams on both the odd-numbered channels and the even-numbered channels of the 64 channels subjected to the 8B/10B conversion, and
the second SDI data streams on both the odd-numbered channels and the even-numbered channels of the 32 channels subjected to the 8B/10B conversion, to thereby generate serial data streams in four lanes as the serial data streams in the plurality of lanes.

3. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to:
map an 8K video signal of 48P-60P/4:2:2/10 bits into one of
first SDI data streams on 32 channels, the first SDI data streams on the 32 channels each conforming to an HD-SDI format, and
second SDI data streams on 16 channels, the second SDI data streams on the 16 channels each conforming to a 3G-SDI format,

perform the 8B/10B conversion in units of 40 bits of the one of
the first SDI data streams on any one of odd-numbered channels and even-numbered channels of the 32 channels, and
the second SDI data streams on any one of odd-numbered channels and even-numbered channels of the 16 channels,

perform scrambling in each of the units of 40 bits of the one
the first SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 32 channels, and
the second SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 16 channels, and

multiplex the one of
the first SDI data streams on both the odd-numbered channels and the even-numbered channels of the 32 channels respectively subjected to corresponding ones of the 8B/10B conversion and the scrambling, and
the second SDI data streams on both the odd-numbered channels and the even-numbered channels of the 16 channels respectively subjected to corresponding ones of the 8B/10B conversion and the scrambling, to thereby generate serial data streams in two lanes as the serial data streams in the plurality of lanes.

4. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to:
map one of
an 8K video signal of 48P-60P/4:4:4/10 bits,
an 8K video signal of 48P-60P/4:4:4/12 bits, and
an 8K video signal of 48P-60P/4:2:2/12 bits into one of
first SDI data streams on 64 channels, the first SDI data streams each conforming to an HD-SDI format, and
second SDI data streams on 32 channels, the second SDI data streams each conforming to a 3G-SDI format,

perform scrambling in units of 40 bits of the one of
the first SDI data streams on any one of odd-numbered channels and even-numbered channels of the 64 channels, and
the second SDI data streams on any one of odd-numbered channels and even-numbered channels of the 32 channels,

extract 32-bit data items from each of the units of 40 bits of the one of
the first SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 64 channels, and
the second SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 32 channels,

perform the 8B/10B conversion of the extracted 32-bit data items, and multiplex the one of
the first SDI data streams on both the odd-numbered channels and the even-numbered channels of the 64 channels respectively subjected to corresponding ones of the scrambling and the 8B/10B conversion, and
the second SDI data streams on both the odd-numbered channels and the even-numbered channels of the 32 channels respectively subjected to corresponding ones of the scrambling and the 8B/10B conversion, to thereby generate serial data streams in four lanes the serial data streams in the plurality of lanes.

5. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to:
map a 4K RAW signal of 48P-60P/4:4:4/16 bits into one of
first SDI data streams on 32 channels, the first SDI data streams on the 32 channels each conforming to an HD-SDI format, and
second SDI data streams on 16 channels, the second SDI data streams on the 16 channels each conforming to a 3G-SDI format,

perform the 8B/10B conversion in units of 40 bits of the one of
the first SDI data streams on any one of odd-numbered channels and even-numbered channels of the 32 channels, and
the second SDI data streams on any one of odd-numbered channels and even-numbered channels of the 16 channels,

extract 32-bit data items from each of the units of 40 bits of the one of
the first SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 32 channels, and
the second SDI data streams on another of the odd-numbered channels and the even-numbered channels of the 16 channels,

perform the 8B/10B conversion of the extracted 32-bit data items, and multiplex the one of
the first SDI data streams on both the odd-numbered channels and the even-numbered channels of the 32 channels subjected to the 8B/10B conversion, and
the second SDI data streams on both the odd-numbered channels and the even-numbered channels of the 16 channels subjected to the 8B/10B conversion, to thereby generate serial data streams in two lanes as the serial data streams in the plurality of lanes.

6. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to map one of
an 8K video signal at 96P-120P and
a 4K video signal at 96P-120P

into the SDI data streams on the plurality of channels in units of two frames.

7. The signal processing apparatus according to claim 1 , wherein the circuitry is configured to:
map one of
an 8K video signal of 50P-60P/4:4:4/10 bits and
an 8K video signal of 50P-60P/4:4:4/12 bits into

Assignees

• Sony Corp

Inventors

• Yamashita Shigeyuki

Classifications

• H04N21/23895

  involving multiplex stream encryption · CPC title

• H04N21/23602 Primary

  Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI · CPC title